Nagendra Krishnapura

66 papers C 16Misc 9Journal 29Unranked 12

Year	Rank	Type	Title / Venue / Authors
2025	J	`jnl`	A 7-bit 1.75-GS/s 6.9-fJ/conv.-step FoMw Loop-Unrolled Fully Asynchronous SAR ADC in 3-nm CMOS for a 224-Gb/s SerDes Receiver. IEEE J. Solid State Circuits Chakravarti Bheemisetti, Karunanidhan Pandey, Idan Lotan, Gadi Ori, Ahmad Khairi, Yoel Krupnik, Udi Virobnik, Subrahmanyam Boyapati, Ariel Cohen, Nagendra Krishnapura
2025	C	`conf`	Design Considerations for a Closed-loop Digital Class-D Audio Amplifier. ISCAS Ananya Senapati, Nagendra Krishnapura
2024	J	`jnl`	A 6 to 12-GHz Fractional-N Frequency Synthesizer With a Digital Technique to Counter Modulus-Dependent Feedback Divider Delays. IEEE J. Solid State Circuits Aditya Narayanan, Abhishek Bhat, Nagendra Krishnapura
2024	C	`conf`	Analysis of Signal Transmission through Time-Varying Inductively Coupled Links. ISCAS Nagendra Krishnapura
2023	—	`conf`	A 17 GHz Output PLL-Based Frequency Doubler with -60dBc Fundamental Spur. APCCAS Soumith Kusumanchi, Srinivas Theertham, Arpan Thakkar, Nagendra Krishnapura
2023	—	`conf`	Bandpass Filter and Oscillator ICs with THD ppd for Testing High-Resolution ADCs. ISSCC Subha Sarkar, Rajat Agarwal, Nagendra Krishnapura
2023	—	`conf`	Settling Time Reduction in a Phase-Locked Loop using Pre-emphasis. APCCAS Sumit Kumar, Nagendra Krishnapura
2023	—	`conf`	Simulation of Divider Phase Noise and Spurious Tones in Integer-N PLLs. ICECS Aditya Narayanan, Nagendra Krishnapura
2022	J	`jnl`	A Reduced-Area Capacitor-Only Loop Filter With Polarity-Switched G IEEE Trans. Circuits Syst. I Regul. Pap. Abhishek Bhat, Nagendra Krishnapura
2022	J	`jnl`	Analysis and Design of a Discrete-Time Delta-Sigma Modulator Using a Cascoded Floating-Inverter-Based Dynamic Amplifier. IEEE J. Solid State Circuits R. S. Ashwin Kumar, Nagendra Krishnapura, Paramita Banerjee
2022	J	`jnl`	Multi-Channel Analog-to-Digital Conversion Using a Delta-Sigma Modulator Without Reset and a Modulated-Sinc-Sum Filter. IEEE Trans. Circuits Syst. I Regul. Pap. R. S. Ashwin Kumar, Nagendra Krishnapura
2021	J	`jnl`	Auto-Zeroing Static Phase Offset in DLLs Using a Digitally Programmable Sensing Circuit. IEEE Trans. Circuits Syst. II Express Briefs Chithra, Aditya Narayanan, R. S. Ashwin Kumar, Nagendra Krishnapura
2021	J	`jnl`	Effects of AC Response Imperfections in True-Time-Delay Lines. IEEE Trans. Circuits Syst. II Express Briefs Imon Mondal, Nagendra Krishnapura
2021	J	`jnl`	Guest Editorial Introduction to the Special Issue on the 2021 IEEE International Solid-State Circuits Conference (ISSCC). IEEE J. Solid State Circuits Yun Chiu, Man-Kay Law, Nagendra Krishnapura, Jason T. Stauth, Jeffrey S. Walling
2020	Misc	`conf`	A 36dB Gain Range, 0.5dB Gain Step Variable Gain Amplifier with 10 to 25MHz Bandwidth Third-Order Filter for Portable Ultrasound Systems. VLSID Purnendu Bhattaru, Nagendra Krishnapura
2020	C	`conf`	A 52dB Spurious-Free Dynamic Range Ku-Band LNA-Mixer in a 130nm SiGe BiCMOS Process. ISCAS Apoorva Bhatia, Yogesh Darwhekar, Subhashish Mukherjee, Samuel Martin, Nagendra Krishnapura
2020	J	`jnl`	A Flexible 18-Channel Multi-Hit Time-to-Digital Converter for Trigger-Based Data Acquisition Systems. IEEE Trans. Circuits Syst. I Regul. Pap. Chithra, Nagendra Krishnapura
2020	J	`jnl`	High Linearity Transmit Power Mixers Using Baseband Current Feedback. IEEE J. Solid State Circuits M. V. Praveen, Nagendra Krishnapura
2020	J	`jnl`	Multi-Channel Analog-to-Digital Conversion Techniques Using a Continuous-Time Delta-Sigma Modulator Without Reset. IEEE Trans. Circuits Syst. R. S. Ashwin Kumar, Nagendra Krishnapura
2020	C	`conf`	Noise Shaping Techniques for SNR Enhancement in SAR Analog to Digital Converters. ISCAS Vipul Bajaj, Anand Kannan, Minkle E. Paul, Nagendra Krishnapura
2019	—	`conf`	A 2-Channel ADC Using a Delta-Sigma Modulator Without Reset & a Modulated-Sinc-Sum Filter. ESSCIRC R. S. Ashwin Kumar, Nagendra Krishnapura
2019	—	`conf`	A 25-to-38GHz, 195dB FoMT LC QVCO in 65nm LP CMOS Using a 4-Port Dual-Mode Resonator for 5G Radios. ISSCC Abhishek Bhat, Nagendra Krishnapura
2019	J	`jnl`	Design Considerations for Low-Distortion Filter and Oscillator ICs for Testing High-Resolution ADCs. IEEE Trans. Circuits Syst. I Regul. Pap. Sangeeta Kumar, Rajashekar Goroju, Dileep Kumar Bhat, K. S. Rakshitdatta, Nagendra Krishnapura
2019	J	`jnl`	Maximizing the Data Rate of an Inductively Coupled Chip-to-Chip Link by Resetting the Channel State Variables. IEEE Trans. Circuits Syst. I Regul. Pap. Nagendra Krishnapura, Anoop Narayan Bhat, Subhashish Mukherjee, Kumar Anurag Shrivastava, Madhulatha Bonu
2019	J	`jnl`	On-Chip Static Phase Difference Measurement Circuit With Gain and Offset Calibration. IEEE Trans. Circuits Syst. II Express Briefs Abhishek Bhat, Nagendra Krishnapura
2019	C	`conf`	Static Phase Offset Reduction Technique for Delay Locked Loops. ISCAS Chithra, Nagendra Krishnapura
2018	C	`conf`	An Automatic LO Leakage Calibration Method for Class-AB Power Mixer Based RF Transmitters. ISCAS M. V. Praveen, Nagendra Krishnapura
2018	J	`jnl`	Expansion and Compression of Analog Pulses by Bandwidth Scaling of Continuous-Time Filters. IEEE Trans. Circuits Syst. I Regul. Pap. Imon Mondal, Nagendra Krishnapura
2018	C	`conf`	Linearity- and Gain-Enhanced Wideband Transconductor Using Digitally Auto-Tuned Negative Conductance Load. ISCAS Imon Mondal, Nagendra Krishnapura
2018	J	`jnl`	Low 1/f IEEE Trans. Circuits Syst. I Regul. Pap. Abhishek Bhat, Nagendra Krishnapura
2018	J	`jnl`	Reset-Free Memoryless Delta-Sigma Analog-to-Digital Conversion. IEEE Trans. Circuits Syst. I Regul. Pap. R. S. Ashwin Kumar, Debasish Behera, Nagendra Krishnapura
2017	—	`conf`	25.4 A 500Mb/s 200pJ/b die-to-die bidirectional link with 24kV surge isolation and 50kV/µs CMR using resonant inductive coupling in 0.18µm CMOS. ISSCC Subhashish Mukherjee, Anoop Narayan Bhat, Kumar Anurag Shrivastava, Madhulatha Bonu, Benjamin Sutton, Venugopal Gopinathan, Ganesan Thiagarajan, Abhijit Patki, Jhankar Malakar, Nagendra Krishnapura
2017	J	`jnl`	A 2-GHz Bandwidth, 0.25-1.7 ns True-Time-Delay Element Using a Variable-Order All-Pass Filter Architecture in 0.13µm CMOS. IEEE J. Solid State Circuits Imon Mondal, Nagendra Krishnapura
2017	Misc	`conf`	A Low Power Multi-channel Input Delta-Sigma ADC without Reset. VLSID Ashwin Kumar Siva Kumar, Debasish Behera, Nagendra Krishnapura
2017	C	`conf`	Optimum scaling of stages in a frequency divider chain for best jitter FoM. ISCAS Sumit Kumar, Nagendra Krishnapura
2017	—	`conf`	Session 12-Analog techniques I. CICC Nagendra Krishnapura, Ken Suyama
2016	J	`jnl`	A 12.5 mW, 11.1 nV√Hz, -115 dB THD, Settling, 18 bit SAR ADC Driver in 0.6 µm CMOS. IEEE Trans. Circuits Syst. II Express Briefs K. S. Rakshitdatta, Yujendra Mitikiri, Nagendra Krishnapura
2016	C	`conf`	A tail-resonance calibration technique for wide tuning range LC VCOs. ISCAS Abhishek Bhat, Nagendra Krishnapura
2016	Misc	`conf`	Demystifying Time Varying Circuits and Systems. VLSID Shanthi Pavan, Nagendra Krishnapura
2015	Misc	`conf`	Accurate Constant Transconductance Generation without Off-Chip Components. VLSID Imon Mondal, Nagendra Krishnapura
2015	C	`conf`	Gain enhanced high frequency OTA with on-chip tuned negative conductance load. ISCAS Imon Mondal, Nagendra Krishnapura
2015	Misc	`conf`	On Slew Rate Enhancement in Class-A Opamps Using Local Common-Mode Feedback. VLSID K. S. Rakshitdatta, Nagendra Krishnapura
2014	—	`conf`	A 2-channel 1MHz BW, 80.5 dB DR ADC using a DS modulator and zero-ISI filter. ESSCIRC Debasish Behera, Nagendra Krishnapura
2014	J	`jnl`	A Model-Agnostic Technique for Simulating Per-Element Distortion Contributions. IEEE Trans. Circuits Syst. I Regul. Pap. Nagendra Krishnapura, K. S. Rakshitdatta
2014	Misc	`conf`	Tutorial T6A: Pedagogy of Negative Feedback Circuits. VLSID Nagendra Krishnapura
2013	—	`conf`	A model-agnostic technique for simulating per-element distortion contributions. CICC Nagendra Krishnapura, K. S. Rakshitdatta
2012	J	`jnl`	A 16 MHz BW 75 dB DR CT ΔΣ ADC Compensated for More Than One Cycle Excess Loop Delay. IEEE J. Solid State Circuits Vikas Singh, Nagendra Krishnapura, Shanthi Pavan, Baradwaj Vigraham, Debasish Behera, Nimit Nigania
2012	C	`conf`	Introducing negative feedback with an integrator as the central element. ISCAS Nagendra Krishnapura
2012	C	`conf`	Synthesis based introduction to opamps and phase locked loops. ISCAS Nagendra Krishnapura
2011	—	`conf`	A 16MHz BW 75dB DR CT ΔΣ ADC compensated for more than one cycle excess loop delay. CICC Vikas Singh, Nagendra Krishnapura, Shanthi Pavan, Baradwaj Vigraham, Nimit Nigania, Debasish Behera
2011	J	`jnl`	A High-IIP3 Third-Order Elliptic Filter With Current-Efficient Feedforward-Compensated Opamps. IEEE Trans. Circuits Syst. II Express Briefs Nagendra Krishnapura, Abhishek Agrawal, Sameer Singh
2011	C	`conf`	Electronic time stretching for fast digitization. ISCAS Nagendra Krishnapura
2011	J	`jnl`	On Pulse Position Modulation and Its Application to PLLs for Spur Reduction. IEEE Trans. Circuits Syst. I Regul. Pap. Chembiyan Thambidurai, Nagendra Krishnapura
2010	C	`conf`	A 100 µW Decimator for a 16 bit 24 kHz bandwidth Audio ΔΣ Modulator. ISCAS Shankar Parameswaran, Nagendra Krishnapura
2010	J	`jnl`	Compensating for Quantizer Delay in Excess of One Clock Cycle in Continuous-Time DeltaSigma Modulators. IEEE Trans. Circuits Syst. II Express Briefs Vikas Singh, Nagendra Krishnapura, Shanthi Pavan
2010	C	`conf`	Efficient determination of feedback DAC errors for digital correction in ΔΣ A/D converters. ISCAS Nagendra Krishnapura
2010	C	`conf`	Spur reduction in wideband PLLs by random positioning of charge pump current pulses. ISCAS Chembiyan Thambidurai, Nagendra Krishnapura
2009	Misc	`conf`	A Comparison of Approaches to Carrier Generation for Zigbee Transceivers. VLSI Design Leburu Manojkumar, Arun Mohan, Nagendra Krishnapura
2009	Misc	`conf`	Negative Feedback System and Circuit Design. VLSI Design Nagendra Krishnapura, Shanthi Pavan
2008	J	`jnl`	A Power Optimized Continuous-Time ΔΣ ADC for Audio Applications. IEEE J. Solid State Circuits Shanthi Pavan, Nagendra Krishnapura, Ramalingam Pandarinathan, Prabu Sankar
2008	Misc	`conf`	Oversampling Analog-to-Digital Converter Design. VLSI Design Shanthi Pavan, Nagendra Krishnapura
2007	—	`conf`	A 90μW 15-bit ΔΣ ADC for digital audio. ESSCIRC Shanthi Pavan, Nagendra Krishnapura, Ramalingam Pandarinathan, Prabu Sankar
2007	J	`jnl`	Automatic Tuning of Time Constants in Continuous-Time Delta-Sigma Modulators. IEEE Trans. Circuits Syst. II Express Briefs Shanthi Pavan, Nagendra Krishnapura
2003	J	`jnl`	Micropower low-voltage analog filter in a digital CMOS process. IEEE J. Solid State Circuits Nagendra Krishnapura, Yannis P. Tsividis
2001	J	`jnl`	Noise and power reduction in filters through the use of adjustable biasing. IEEE J. Solid State Circuits Nagendra Krishnapura, Yannis P. Tsividis
2000	J	`jnl`	A 5.3-GHz programmable divider for HiPerLAN in 0.25-μm CMOS. IEEE J. Solid State Circuits Nagendra Krishnapura, Peter R. Kinget