Nagarajan Ranganathan

100 papers A 6B 1C 6Misc 16Journal 43Unranked 26

Year	Rank	Type	Title / Venue / Authors
2018	J	`jnl`	A System Architecture for the Detection of Insider Attacks in Big Data Systems. IEEE Trans. Dependable Secur. Comput. Santosh Aditham, Nagarajan Ranganathan
2017	J	`jnl`	Design of Efficient Reversible Logic Based Binary and BCD Adder Circuits. CoRR Himanshu Thapliyal, Nagarajan Ranganathan
2017	—	`conf`	LSTM-Based Memory Profiling for Predicting Data Attacks in Distributed Big Data Systems. IPDPS Workshops Santosh Aditham, Nagarajan Ranganathan, Srinivas Katkoori
2016	J	`jnl`	A Novel Control-flow based Intrusion Detection Technique for Big Data Systems. CoRR Santosh Aditham, Nagarajan Ranganathan
2016	J	`jnl`	A System Architecture for the Detection of Insider Attacks in Big Data Systems. CoRR Santosh Aditham, Nagarajan Ranganathan
2016	J	`jnl`	Call Trace and Memory Access Pattern based Runtime Insider Threat Detection for Big Data Platforms. CoRR Santosh Aditham, Nagarajan Ranganathan, Srinivas Katkoori
2016	J	`jnl`	Enabling New Computation Paradigms with HyperFET - An Emerging Device. IEEE Trans. Multi Scale Comput. Syst. Wei-Yu Tsai, Xueqing Li, Matthew Jerry, Baihua Xie, Nikhil Shukla, Huichu Liu, Nandhini Chandramoorthy, Matthew Cotter, Arijit Raychowdhury, Donald M. Chiarulli, Steven P. Levitan, Suman Datta, John Sampson, Nagarajan Ranganathan, Vijaykrishnan Narayanan
2016	—	`conf`	Memory access pattern based insider threat detection in big data systems. IEEE BigData Santosh Aditham, Nagarajan Ranganathan, Srinivas Katkoori
2015	—	`conf`	A novel framework for mitigating insider attacks in big data systems. IEEE BigData Santosh Aditham, Nagarajan Ranganathan
2015	—	`conf`	An energy-aware scheduling heuristic for distributed systems using non-cooperative games. IGSC Santosh Aditham, Nagarajan Ranganathan
2015	J	`jnl`	Design of Adiabatic Dynamic Differential Logic for DPA-Resistant Secure Integrated Circuits. IEEE Trans. Very Large Scale Integr. Syst. Matthew A. Morrison, Nagarajan Ranganathan, Jay Ligatti
2015	A	`conf`	GTFUZZ: a novel algorithm for robust dynamic power optimization via gate sizing with fuzzy games. DATE Tony Casagrande, Nagarajan Ranganathan
2015	J	`jnl`	Reversible logic based multiplication computing unit using binary tree data structure. J. Supercomput. Saurabh Kotiyal, Himanshu Thapliyal, Nagarajan Ranganathan
2014	—	`conf`	A Feedback, Runtime Technique for Scaling the Frequency in GPU Architectures. ISVLSI Yue Wang, Nagarajan Ranganathan
2014	Misc	`conf`	Circuit for Reversible Quantum Multiplier Based on Binary Tree Optimizing Ancilla and Garbage Bits. VLSID Saurabh Kotiyal, Himanshu Thapliyal, Nagarajan Ranganathan
2014	J	`jnl`	Design of Reversible Adder-Subtractor and its Mapping in Optical Computing Domain. Trans. Comput. Sci. Saurabh Kotiyal, Himanshu Thapliyal, Nagarajan Ranganathan
2014	J	`jnl`	Efficient reversible NOR gates and their mapping in optical computing domain. Microelectron. J. Saurabh Kotiyal, Himanshu Thapliyal, Nagarajan Ranganathan
2014	Misc	`conf`	Forward Body Biased Adiabatic Logic for Peak and Average Power Reduction in 22nm CMOS. VLSID Matthew Morrison, Nagarajan Ranganathan
2014	—	`ch.`	Reversible Logic Based Design and Test of Field Coupled Nanocomputing Circuits. Field-Coupled Nanocomputing Himanshu Thapliyal, Nagarajan Ranganathan, Saurabh Kotiyal
2014	J	`jnl`	Synthesis of Dual-Rail Adiabatic Logic for Low Power Security Applications. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. Matthew Morrison, Nagarajan Ranganathan
2014	—	`ed.`	Transactions on Computational Science XXIV - Special Issue on Reversible Computing Trans. Comput. Sci. Marina L. Gavrilova, C. J. Kenneth Tan, Himanshu Thapliyal, Nagarajan Ranganathan
2013	J	`jnl`	A Clock Control Strategy for Peak Power and RMS Current Reduction Using Path Clustering. IEEE Trans. Very Large Scale Integr. Syst. Ransford Hyman Jr., Nagarajan Ranganathan, Thomas Bingel, Deanne Tran Vo
2013	—	`conf`	A new CRL gate as super class of Fredkin gate to design reversible quantum circuits. MWSCAS Himanshu Thapliyal, Apeksha Bhatt, Nagarajan Ranganathan
2013	—	`conf`	A novel optimization method for reversible logic circuit minimization. ISVLSI Matthew Morrison, Nagarajan Ranganathan
2013	—	`conf`	Behavioral model of integrated qubit gates for quantum reversible logic design. ISVLSI Matthew Lewandowski, Nagarajan Ranganathan, Matthew Morrison
2013	J	`jnl`	Design of Testable Reversible Sequential Circuits. IEEE Trans. Very Large Scale Integr. Syst. Himanshu Thapliyal, Nagarajan Ranganathan, Saurabh Kotiyal
2013	J	`jnl`	Design of efficient reversible logic-based binary and BCD adder circuits. ACM J. Emerg. Technol. Comput. Syst. Himanshu Thapliyal, Nagarajan Ranganathan
2013	J	`jnl`	Guest editorial - Design methodologies for nanoelectronic digital and analogue circuits. IET Circuits Devices Syst. Sandip Kundu, Saraju P. Mohanty, Nagarajan Ranganathan
2012	—	`conf`	Analysis of Reversible Logic Based Sequential Computing Structures Using Quantum Mechanics Principles. ISVLSI Matthew Morrison, Nagarajan Ranganathan
2012	—	`conf`	Design of a Tree-Based Comparator and Memory Unit Based on a Novel Reversible Logic Structure. ISVLSI Matthew Morrison, Matthew Lewandowski, Nagarajan Ranganathan
2012	—	`conf`	Design, Synthesis and Test of Reversible Circuits for Emerging Nanotechnologies. ISVLSI Himanshu Thapliyal, Nagarajan Ranganathan
2012	J	`jnl`	Dynamic clock stretching for variation compensation in VLSI circuit design. ACM J. Emerg. Technol. Comput. Syst. Venkataraman Mahalingam, Nagarajan Ranganathan, Ransford Hyman Jr.
2012	—	`conf`	Mach-Zehnder Interferometer Based All Optical Reversible NOR Gates. ISVLSI Saurabh Kotiyal, Himanshu Thapliyal, Nagarajan Ranganathan
2012	A	`conf`	Mach-Zehnder interferometer based design of all optical reversible binary adder. DATE Saurabh Kotiyal, Himanshu Thapliyal, Nagarajan Ranganathan
2012	A	`conf`	Run-time power-gating in caches of GPUs for leakage energy savings. DATE Yue Wang, Soumyaroop Roy, Nagarajan Ranganathan
2012	Misc	`conf`	Tutorial T2: Reversible Logic: Fundamentals and Applications in Ultra-Low Power, Fault Testing and Emerging Nanotechnologies, and Challenges in Future. VLSI Design Himanshu Thapliyal, Nagarajan Ranganathan
2011	J	`jnl`	A Utilitarian Approach to Variation Aware Delay, Power, and Crosstalk Noise Optimization. IEEE Trans. Very Large Scale Integr. Syst. Upavan Gupta, Nagarajan Ranganathan
2011	—	`conf`	Design of a Reversible ALU Based on Novel Programmable Reversible Logic Gate Structures. ISVLSI Matthew Morrison, Nagarajan Ranganathan
2011	J	`jnl`	Redundancy Mining for Soft Error Detection in Multicore Processors. IEEE Trans. Computers Ransford Hyman Jr., Koustav Bhattacharya, Nagarajan Ranganathan
2011	J	`jnl`	Reversible Logic Based Concurrent Error Detection Methodology For Emerging Nanocircuits CoRR Himanshu Thapliyal, Nagarajan Ranganathan
2011	J	`jnl`	State-Retentive Power Gating of Register Files in Multicore Processors Featuring Multithreaded In-Order Cores. IEEE Trans. Computers Soumyaroop Roy, Nagarajan Ranganathan, Srinivas Katkoori
2010	J	`jnl`	A Game Theoretic Approach for Simultaneous Compaction and Equipartitioning of Spatial Data Sets. IEEE Trans. Knowl. Data Eng. Upavan Gupta, Nagarajan Ranganathan
2010	Misc	`conf`	Design of Reversible Latches Optimized for Quantum Cost, Delay and Garbage Outputs. VLSI Design Himanshu Thapliyal, Nagarajan Ranganathan
2010	J	`jnl`	Design of reversible sequential circuits optimizing quantum cost, delay, and garbage outputs. ACM J. Emerg. Technol. Comput. Syst. Himanshu Thapliyal, Nagarajan Ranganathan
2009	J	`jnl`	A Framework for Correction of Multi-Bit Soft Errors in L2 Caches Based on Redundancy. IEEE Trans. Very Large Scale Integr. Syst. Koustav Bhattacharya, Nagarajan Ranganathan, Soontae Kim
2009	J	`jnl`	A Framework for Power-Gating Functional Units in Embedded Microprocessors. IEEE Trans. Very Large Scale Integr. Syst. Soumyaroop Roy, Nagarajan Ranganathan, Srinivas Katkoori
2009	—	`conf`	A New Placement Algorithm for Reduction of Soft Errors in Macrocell Based Design of Nanometer Circuits. ISVLSI Koustav Bhattacharya, Nagarajan Ranganathan
2009	C	`conf`	A VLSI System Architecture for Optical Flow Computation. ISCAS Koustav Bhattacharya, Venkataraman Mahalingam, Nagarajan Ranganathan
2009	—	`conf`	A unified gate sizing formulation for optimizing soft error rate, cross-talk noise and power under process variations. ISQED Koustav Bhattacharya, Nagarajan Ranganathan
2009	C	`conf`	Compiler-directed leakage reduction in embedded microprocessors. ICCD Soumyaroop Roy, Nagarajan Ranganathan, Srinivas Katkoori
2009	C	`conf`	Concurrently Testable FPGA Design for Molecular QCA using Conservative Reversible Logic Gate. ISCAS Himanshu Thapliyal, Nagarajan Ranganathan
2009	Misc	`conf`	Conservative QCA Gate (CQCA) for Designing Concurrently Testable Molecular QCA Circuits. VLSI Design Himanshu Thapliyal, Nagarajan Ranganathan
2009	—	`conf`	Design of Efficient Reversible Binary Subtractors Based on a New Reversible Gate. ISVLSI Himanshu Thapliyal, Nagarajan Ranganathan
2009	C	`conf`	Exploring Compiler Optimizations for Enhancing Power Gating. ISCAS Soumyaroop Roy, Nagarajan Ranganathan, Srinivas Katkoori
2009	Misc	`conf`	RADJAM: A Novel Approach for Reduction of Soft Errors in Logic Circuits. VLSI Design Koustav Bhattacharya, Nagarajan Ranganathan
2009	J	`jnl`	Variation-aware multimetric optimization during gate sizing. ACM Trans. Design Autom. Electr. Syst. Nagarajan Ranganathan, Upavan Gupta, Venkataraman Mahalingam
2008	—	`conf`	A Fuzzy Approach for Variation Aware Buffer Insertion and Driver Sizing. ISVLSI Venkataraman Mahalingam, Nagarajan Ranganathan
2008	—	`conf`	A linear programming formulation for security-aware gate sizing. ACM Great Lakes Symposium on VLSI Koustav Bhattacharya, Nagarajan Ranganathan
2008	B	`conf`	A microeconomic approach to multi-objective spatial clustering. ICPR Upavan Gupta, Nagarajan Ranganathan
2008	A	`conf`	An expected-utility based approach to variation aware VLSI optimization under scarce information. ISLPED Upavan Gupta, Nagarajan Ranganathan
2008	A	`conf`	Reliability-centric gate sizing with simultaneous optimization of soft error rate, delay and power. ISLPED Koustav Bhattacharya, Nagarajan Ranganathan
2007	Misc	`conf`	A Compiler Based Leakage Reduction Technique by Power-Gating Functional Units in Embedded Microprocessors. VLSI Design Soumyaroop Roy, Srinivas Katkoori, Nagarajan Ranganathan
2007	J	`jnl`	A Sequential Distinguisher for Covert Channel Identification. Int. J. Netw. Secur. K. P. Subbalakshmi, Rajarathnam Chandramouli, Nagarajan Ranganathan
2007	A	`conf`	A microeconomic approach to multi-robot team formation. IROS Upavan Gupta, Nagarajan Ranganathan
2007	C	`conf`	Improving the reliability of on-chip L2 cache using redundancy. ICCD Koustav Bhattacharya, Soontae Kim, Nagarajan Ranganathan
2007	—	`conf`	Integrated Gate and Wire Sizing at Post Layout Level. ISVLSI Narender Hanchate, Nagarajan Ranganathan
2007	J	`jnl`	Multievent Crisis Management Using Noncooperative Multistep Games. IEEE Trans. Computers Upavan Gupta, Nagarajan Ranganathan
2007	—	`conf`	Statistical Gate Sizing for Yield Enhancement at Post Layout Level. ISVLSI Narender Hanchate, Nagarajan Ranganathan
2007	J	`jnl`	VLSI architecture and chip for combined invisible robust and fragile watermarking. IET Comput. Digit. Tech. Saraju P. Mohanty, Elias Kougianos, Nagarajan Ranganathan
2006	Misc	`conf`	A Linear Time Algorithm for Wire Sizing with Simultaneous Optimization of Interconnect Delay and Crosstalk Noise. VLSI Design Narender Hanchate, Nagarajan Ranganathan
2006	J	`jnl`	A dual voltage-frequency VLSI chip for image watermarking in DCT domain. IEEE Trans. Circuits Syst. II Express Briefs Saraju P. Mohanty, Nagarajan Ranganathan, Karthikeyan Balakrishnan
2006	J	`jnl`	A game-theoretic framework for multimetric optimization of interconnect delay, power, and crosstalk noise during wire sizing. ACM Trans. Design Autom. Electr. Syst. Narender Hanchate, Nagarajan Ranganathan
2006	Misc	`conf`	An Automatic Code Generation Tool for Partitioned Software in Distributed Systems. VLSI Design Viswanath Sairaman, Nagarajan Ranganathan, Neeta S. Singh
2006	—	`conf`	CHESS: A Comprehensive Tool for CDFG Extraction and Synthesis of Low Power Designs from VHDL. ISVLSI Nagarajan Ranganathan, Ravi Namballa, Narender Hanchate
2006	J	`jnl`	Improving Accuracy in Mitchell's Logarithmic Multiplication Using Operand Decomposition. IEEE Trans. Computers Venkataraman Mahalingam, Nagarajan Ranganathan
2006	Misc	`conf`	Leakage Power Reduction in Dual-Vdd and Dual-Vth Designs through Probabilistic Analysis of Vth Variation. VLSI Design Aswath Oruganti, Nagarajan Ranganathan
2006	—	`conf`	Post-Layout Gate Sizing for Interconnect Delay and Crosstalk Noise Optimization. ISQED Narender Hanchate, Nagarajan Ranganathan
2006	J	`jnl`	Simultaneous Interconnect Delay and Crosstalk Noise Optimization through Gate Sizing Using Game Theory. IEEE Trans. Computers Narender Hanchate, Nagarajan Ranganathan
2005	J	`jnl`	A VLSI architecture for visible watermarking in a secure still digital camera (S IEEE Trans. Very Large Scale Integr. Syst. Saraju P. Mohanty, Nagarajan Ranganathan, Ravi Namballa
2005	J	`jnl`	A VLSI architecture for watermarking in a secure still digital camera (S IEEE Trans. Very Large Scale Integr. Syst. Saraju P. Mohanty, Nagarajan Ranganathan, Ravi Namballa
2004	Misc	`conf`	A New Technique for Leakage Reduction in CMOS Circuits using Self-Controlled Stacked Transistors. VLSI Design Narender Hanchate, Nagarajan Ranganathan
2004	J	`jnl`	A framework for energy and transient power reduction during behavioral synthesis. IEEE Trans. Very Large Scale Integr. Syst. Saraju P. Mohanty, Nagarajan Ranganathan
2004	—	`conf`	Control and Data Flow Graph Extraction for High-Level Synthesis. ISVLSI Ravi Namballa, Nagarajan Ranganathan, Abdel Ejnioui
2004	Misc	`conf`	ILP Models for Energy and Transient Power Minimization During Behavioral Synthesis. VLSI Design Saraju P. Mohanty, Nagarajan Ranganathan, Sunil K. Chappidi
2004	J	`jnl`	LECTOR: a technique for leakage reduction in CMOS circuits. IEEE Trans. Very Large Scale Integr. Syst. Narender Hanchate, Nagarajan Ranganathan
2004	Misc	`conf`	VLSI Implementation of Visible Watermarking for a Secure Digital Still Camera Design. VLSI Design Saraju P. Mohanty, Nagarajan Ranganathan, Ravi Namballa
2003	—	`conf`	Transient power minimization through datapath scheduling in multiple supply voltage environment. ICECS Saraju P. Mohanty, Nagarajan Ranganathan, Sunil K. Chappidi
2000	J	`jnl`	VBR video traffic management using a predictor-based architecture. Comput. Commun. Girish Chiruvolu, Ravi Sankar, Nagarajan Ranganathan
1999	Misc	`conf`	Context modeling of wavelet coefficients in EZW-based lossless image coding. ICASSP Veeraraghavan N. Ramaswamy, Kamesh Namuduri, Nagarajan Ranganathan
1998	Misc	`conf`	A VLSI ATM Switch Architecture for VBR Traffic. VLSI Design Nagarajan Ranganathan, Rajat Anand, Girish Chiruvolu
1998	J	`jnl`	A linear array processor with dynamic frequency clocking for image processing applications. IEEE Trans. Circuits Syst. Video Technol. Nagarajan Ranganathan, Narayanan Vijaykrishnan, N. Bhavanishankar
1998	C	`conf`	An adaptive scheme for better utilization with QoS constraints for VBR video traffic in ATM networks. ISCC Girish Chiruvolu, Ravi Sankar, Nagarajan Ranganathan
1996	Misc	`conf`	A linear systolic algorithm and architecture for convex bipartite matching. HiPC Nagarajan Ranganathan, Rajesh Chandra
1996	—	`conf`	DFLAP: a dynamic frequency linear array processor. ICIP (2) Narayanan Vijaykrishnan, Nagarajan Ranganathan, N. Bhavanishankar
1995	J	`jnl`	A high speed systolic architecture for labeling connected components in an image. IEEE Trans. Syst. Man Cybern. Nagarajan Ranganathan, Rajiv Mehrotra, S. Subramaniam
1995	J	`jnl`	A lossless image compression algorithm using variable block size segmentation. IEEE Trans. Image Process. Nagarajan Ranganathan, Steve G. Romaniuk, Kameswara Rao Namuduri
1994	J	`jnl`	Efficient computation of gabor filter based multiresolution responses. Pattern Recognit. Kameswara Rao Namuduri, Rajiv Mehrotra, Nagarajan Ranganathan
1992	J	`jnl`	Gabor filter-based edge detection. Pattern Recognit. Rajiv Mehrotra, Kameswara Rao Namuduri, Nagarajan Ranganathan
1991	—	`conf`	A high speed systolic architecture for labeling connected components in an image. SPDP Nagarajan Ranganathan, Rajiv Mehrotra, S. Subramaniam
1990	J	`jnl`	Corner detection. Pattern Recognit. Rajiv Mehrotra, Sanjay Nichani, Nagarajan Ranganathan