Nadine Azémard

63 papers A 2C 3Journal 23Unranked 33

Year	Rank	Type	Title / Venue / Authors
2025	J	`jnl`	Lagrange Oscillatory Neural Networks for Constraint Satisfaction and Optimization. CoRR Corentin Delacour, Bram Haverkort, Filip Sabo, Nadine Azémard, Aida Todri-Sanial
2025	J	`jnl`	Lagrange oscillatory neural networks for constraint satisfaction and optimization. Neuromorph. Comput. Eng. Corentin Delacour, Bram Haverkort, Filip Sabo, Nadine Azémard, Aida Todri-Sanial
2023	J	`jnl`	A mixed-signal oscillatory neural network for scalable analog computations in phase domain. Neuromorph. Comput. Eng. Corentin Delacour, Stefania Carapezzi, Gabriele Boschetto, Madeleine Abernot, Thierry Gil, Nadine Azémard, Aida Todri-Sanial
2021	—	`conf`	Iterative Method for Performance Prediction Improvement of Integrated Circuits. DCIS Gwenael Chaillou, Philippe Maurine, Jean-Marc Gallière, Nadine Azémard
2021	—	`conf`	Oscillatory Neural Networks for Edge AI Computing. ISVLSI Corentin Delacour, Stefania Carapezzi, Madeleine Abernot, Gabriele Boschetto, Nadine Azémard, Jérémie Salles, Thierry Gil, Aida Todri-Sanial
2019	J	`jnl`	Energy Autonomous Wearable Sensors for Smart Healthcare: A Review. CoRR Abhishek Singh Dahiya, Jerome Thireau, Jamila Boudaden, Swatchith Lal, Umair Gulzar, Yan Zhang, Thierry Gil, Nadine Azémard, Peter Ramm, Tim Kiessling, Cian O'Murchu, Fredrik Sebelius, Jonas Tilly, Colm Glynn, Shane Geary, Colm O'Dwyer, Kafil Razeeb, Alain Lacampagne, Benoît Charlot, Aida Todri-Sanial
2018	—	`conf`	Combined Analysis of Supply Voltage and Body-Bias Voltage for Energy Management. PATMOS Rida Kheirallah, Jean-Marc Gallière, Nadine Azémard, Gilles R. Ducharme
2017	—	`conf`	Synchronised 4-Phase Resonant Power Clock Supply for Energy Efficient Adiabatic Logic. ICRC Nicolas Jeanniot, Gaël Pillonnet, Pascal Nouet, Nadine Azémard, Aida Todri-Sanial
2016	J	`jnl`	Energy Study for 28 nm Fully Depleted Silicon-On-Insulator Devices. J. Low Power Electron. Rida Kheirallah, Gilles R. Ducharme, Nadine Azémard
2016	J	`jnl`	Selected Articles from the 6th International Workshop on CMOS Variability, Salvador, Bahia, Brazil, September 1-4, 2015. J. Low Power Electron. Ricardo Reis, Nadine Azémard
2015	J	`jnl`	Selected Articles from the 5th European Workshop on CMOS Variability, Palma (Mallorca), Spain, September 29-October 1, 2014. J. Low Power Electron. Nadine Azémard, Eugeni García-Moreno
2014	J	`jnl`	Selected Peer-Reviewed Articles from the 4th European Workshop on CMOS Variability, Karlsruhe, Germany, September 9-11, 2013. J. Low Power Electron. Nadine Azémard, Jörg Henkel
2012	J	`jnl`	Delay-correlation-aware SSTA based on conditional moments. Microelectron. J. Zeqin Wu, Philippe Maurine, Nadine Azémard, Gilles R. Ducharme
2012	J	`jnl`	Selected Articles from the VARI 2011 Workshop. J. Low Power Electron. Nadine Azémard, Marc Belleville
2012	J	`jnl`	Selected Articles from the VARI 2012 Workshop. J. Low Power Electron. Nadine Azémard, Gilles Jacquemod
2012	—	`conf`	Statistical timing characterization. ISSoC Zeqin Wu, Philippe Maurine, Nadine Azémard, Gilles R. Ducharme
2011	J	`jnl`	Timing slack monitoring under process and environmental variations: Application to a DSP performance optimization. Microelectron. J. Bettina Rebaud, Marc Belleville, Edith Beigné, Christian Bernard, Michel Robert, Philippe Maurine, Nadine Azémard
2010	J	`jnl`	On-Chip Process Variability Monitoring Flow. J. Low Power Electron. Nabila Moubdi, Philippe Maurine, Robin Wilson, Sylvain Engels, Nadine Azémard, Vincent Dumettier, Pierre Busson
2010	J	`jnl`	Selected Peer-Reviewed Articles from the VARI 2010 Workshop. J. Low Power Electron. Nadine Azémard
2009	—	`conf`	Digital Timing Slack Monitors and Their Specific Insertion Flow for Adaptive Compensation of Variabilities. PATMOS Bettina Rebaud, Marc Belleville, Edith Beigné, Christian Bernard, Michel Robert, Philippe Maurine, Nadine Azémard
2009	—	`conf`	Interpreting SSTA Results with Correlation. PATMOS Zeqin Wu, Philippe Maurine, Nadine Azémard, Gilles R. Ducharme
2009	—	`conf`	Product On-Chip Process Compensation for Low Power and Yield Enhancement. PATMOS Nabila Moubdi, Philippe Maurine, Robin Wilson, Nadine Azémard, Vincent Dumettier, Abhishek Bansal, Sebastien Barasinski, Alain Tournier, Guy Durieu, David Meyer, Pierre Busson, Sarah Verhaeren, Sylvain Engels
2009	J	`jnl`	Timing margin evaluation with a simple statistical timing analysis flow. J. Embed. Comput. Vincent Migairou, Robin Wilson, Sylvain Engels, Zeqin Wu, Nadine Azémard, Philippe Maurine
2008	J	`jnl`	Editorial. Integr. Nadine Azémard, Philippe Maurine, Johan Vounckx
2008	—	`conf`	SSTA considering switching process induced correlations. APCCAS Zeqin Wu, Philippe Maurine, Nadine Azémard, Gilles R. Ducharme
2008	—	`conf`	Setup and Hold Timing Violations Induced by Process Variations, in a Digital Multiplier. ISVLSI Bettina Rebaud, Marc Belleville, Christian Bernard, Zeqin Wu, Michel Robert, Philippe Maurine, Nadine Azémard
2007	—	`conf`	A Simple Statistical Timing Analysis Flow and Its Application to Timing Margin Evaluation. PATMOS Vincent Migairou, Robin Wilson, Sylvain Engels, Zeqin Wu, Nadine Azémard, Philippe Maurine
2007	—	`ed.`	Integrated Circuit and System Design. Power and Timing Modeling, Optimization and Simulation, 17th International Workshop, PATMOS 2007, Gothenburg, Sweden, September 3-5, 2007, Proceedings PATMOS Nadine Azémard, Lars J. Svensson
2007	J	`jnl`	Low Power Oriented CMOS Circuit Optimization Protocol CoRR Alexandre Verle, Xavier Michel, Nadine Azémard, Philippe Maurine, Daniel Auvergne
2007	A	`conf`	Temperature and voltage aware timing analysis: application to voltage drops. DATE B. Lasbouygues, Robin Wilson, Nadine Azémard, Philippe Maurine
2007	J	`jnl`	Temperature- and Voltage-Aware Timing Analysis. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. B. Lasbouygues, Robin Wilson, Nadine Azémard, Philippe Maurine
2006	J	`jnl`	A comprehensive performance macro-modeling of on-chip RC interconnects considering line shielding effects. Integr. Sylvain Engels, Robin Wilson, Nadine Azémard, Philippe Maurine
2006	C	`conf`	Circuit sizing method under delay constraint. ISCAS Alexandre Verle, A. Landrault, Philippe Maurine, Nadine Azémard
2006	—	`ed.`	Integrated Circuit and System Design. Power and Timing Modeling, Optimization and Simulation, 16th International Workshop, PATMOS 2006, Montpellier, France, September 13-15, 2006, Proceedings PATMOS Johan Vounckx, Nadine Azémard, Philippe Maurine
2006	J	`jnl`	Logical effort model extension to propagation delay representation. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. B. Lasbouygues, Sylvain Engels, Robin Wilson, Philippe Maurine, Nadine Azémard, Daniel Auvergne
2006	—	`conf`	Request-skip adders : CMOS standard cell data dependent adders. ICECS Robin Perrot, Nadine Azémard, Philippe Maurine
2006	—	`conf`	Statistical Characterization of Library Timing Performance. PATMOS Vincent Migairou, Robin Wilson, Sylvain Engels, Nadine Azémard, Philippe Maurine
2006	—	`conf`	Timing analysis in presence of supply voltage and temperature variations. ISPD B. Lasbouygues, Robin Wilson, Nadine Azémard, Philippe Maurine
2005	—	`conf`	Circuit optimization based on speed indicators. ICECS Alexandre Verle, A. Landrault, Philippe Maurine, Nadine Azémard
2005	A	`conf`	Low Power Oriented CMOS Circuit Optimization Protocol. DATE Alexandre Verle, Xavier Michel, Nadine Azémard, Philippe Maurine, Daniel Auvergne
2005	—	`conf`	Speed Indicators for Circuit Optimization. PATMOS Alexandre Verle, A. Landrault, Philippe Maurine, Nadine Azémard
2005	—	`conf`	Temperature Dependency in UDSM Process. PATMOS B. Lasbouygues, Robin Wilson, Nadine Azémard, Philippe Maurine
2004	—	`conf`	Delay bound based CMOS gate sizing technique. ISCAS (5) Alexandre Verle, Xavier Michel, Philippe Maurine, Nadine Azémard, Daniel Auvergne
2004	—	`conf`	Design Optimization with Automated Cell Generation. PATMOS A. Landrault, Nadine Azémard, Philippe Maurine, Michel Robert, Daniel Auvergne
2004	—	`conf`	Performance Metric Based Optimization Protocol. PATMOS Xavier Michel, Alexandre Verle, Philippe Maurine, Nadine Azémard, Daniel Auvergne
2004	—	`conf`	Physical Extension of the Logical Effort Model. PATMOS B. Lasbouygues, Robin Wilson, Philippe Maurine, Nadine Azémard, Daniel Auvergne
2004	—	`conf`	Temperature Dependence in Low Power CMOS UDSM Process. PATMOS B. Lasbouygues, Robin Wilson, Philippe Maurine, Nadine Azémard, Daniel Auvergne
2003	—	`conf`	CMOS Gate Sizing under Delay Constraint. PATMOS Alexandre Verle, Xavier Michel, Philippe Maurine, Nadine Azémard, Daniel Auvergne
2003	—	`conf`	Continuous representation of the performance of a CMOS library. ESSCIRC B. Lasbouygues, Joel Schindler, Sylvain Engels, Philippe Maurine, Nadine Azémard, Daniel Auvergne
2003	—	`conf`	Metric Definition for Circuit Speed Optimization. PATMOS Xavier Michel, Alexandre Verle, Nadine Azémard, Philippe Maurine, Daniel Auvergne
2002	—	`conf`	Gate speed improvement at minimal power dissipation. APCCAS (2) Philippe Maurine, Xavier Michel, Nadine Azémard, Daniel Auvergne
2002	—	`conf`	Structure Independent Representation of Output Transition Time for CMOS Library. PATMOS Philippe Maurine, Nadine Azémard, Daniel Auvergne
2002	J	`jnl`	Transition time modeling in deep submicron CMOS. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. Philippe Maurine, Mustapha Rezzoug, Nadine Azémard, Daniel Auvergne
2001	—	`conf`	Delay bound determination for timing closure satisfaction. ISCAS (5) Nadine Azémard, M. Aline, Daniel Auvergne
2001	C	`conf`	Feasible Delay Bound Definition. VLSI-SOC Nadine Azémard, M. Aline, Philippe Maurine, Daniel Auvergne
2001	C	`conf`	Gate Sizing for Low Power Design. VLSI-SOC Philippe Maurine, Nadine Azémard, Daniel Auvergne
2001	J	`jnl`	POPS: A tool for delay/power performance optimization. J. Syst. Archit. Nadine Azémard, Daniel Auvergne
1999	—	`conf`	Delay-power performance analysis. ICECS S. Cremoux, M. Aline, Nadine Azémard, Daniel Auvergne
1996	—	`conf`	Design and selection of buffers for minimum power-delay product. ED&TC S. Turgis, Nadine Azémard, Daniel Auvergne
1995	—	`conf`	Explicit evaluation of short circuit power dissipation for CMOS logic structures. ISLPD S. Turgis, Nadine Azémard, Daniel Auvergne
1992	—	`conf`	P.SIZE: a sizing aid for optimized designs. EURO-DAC Nadine Azémard, V. Bonzom, Daniel Auvergne
1991	—	`conf`	Formal sizing rules of CMOS circuits. EURO-DAC Daniel Auvergne, Nadine Azémard, V. Bonzom, Denis Deschacht, Michel Robert
1990	J	`jnl`	Input waveform slope effects in CMOS delays. IEEE J. Solid State Circuits Daniel Auvergne, Nadine Azémard, Denis Deschacht, Michel Robert