Nader Rafla - RankMe

24 papers A 3B 1C 1Misc 1Journal 5Unranked 13

Year	Rank	Type	Title / Venue / Authors
2024	—	`conf`	Enhanced Hardware Trojan Detection in Chips By Reducing Linearity Between Features. MWSCAS Alfred Moussa, Nader Rafla
2024	—	`conf`	Hardware Implementation of Image Processing Morphological and Convolution Operations as SoC on FPGAs. DMIP Alfred M. Moussa, Richard Groves, Nader Rafla
2023	J	`jnl`	SoC Reconfigurable Architecture for Implementing Software Trained Recurrent Neural Networks on FPGA. IEEE Trans. Circuits Syst. I Regul. Pap. Michael R. Wasef, Nader Rafla
2022	J	`jnl`	Efficient mitigation technique for Black Hole router attack in Network-on-Chip. Microprocess. Microsystems Luka Daoud, Nader Rafla
2022	—	`conf`	Energy-Efficient Black Hole Router Detection in Network-on-Chip. SOCC Luka Daoud, Nader Rafla
2021	—	`conf`	Hardware implementation of Multi-Rate input SoftMax activation function. MWSCAS Michael R. Wasef, Nader Rafla
2020	J	`jnl`	A fully pipelined FPGA accelerator for scale invariant feature transform keypoint descriptor matching, . CoRR Luka Daoud, Muhammad Kamran Latif, H. S. Jacinto, Nader Rafla
2020	J	`jnl`	A fully pipelined FPGA accelerator for scale invariant feature transform keypoint descriptor matching. Microprocess. Microsystems Luka Daoud, Muhammad Kamran Latif, H. S. Jacinto, Nader Rafla
2020	J	`jnl`	A reconfigurable HexCell-based systolic array architecture for evolvable hardware on FPGA. Microprocess. Microsystems Fady Hussein, Luka Daoud, Nader Rafla
2020	B	`conf`	Evaluating and Improving Child-Directed Automatic Speech Recognition. LREC Eric G. Booth, Jake Carns, Casey Kennington, Nader Rafla
2020	C	`conf`	HLS Implementation of Linear Discriminant Analysis Classifier. ISCAS Michael R. Wasef, Nader Rafla
2019	—	`conf`	Analysis of Black Hole Router Attack in Network-on-Chip. MWSCAS Luka Daoud, Nader Rafla
2019	—	`conf`	Detection and prevention protocol for black hole attack in network-on-chip. NOCS Luka Daoud, Nader Rafla
2019	Misc	`conf`	Optimization of Advanced Encryption Standard (AES) Using Vivado High Level Synthesis (HLS). CATA Luka Daoud, Fady Hussein, Nader Rafla
2019	—	`conf`	Runtime Packet-Dropping Detection of Faulty Nodes in Network-on-Chip. SoCC Luka Daoud, Nader Rafla
2018	A	`conf`	HexCell: a Hexagonal Cell for Evolvable Systolic Arrays on FPGAs: (Abstract Only). FPGA Fady Hussein, Luka Daoud, Nader Rafla
2018	—	`conf`	Optimization of a Quantum-Secure Sponge-Based Hash Message Authentication Protocol. MWSCAS Muhammad Kamran Latif, H. S. Jacinto, Luka Daoud, Nader Rafla
2018	—	`conf`	Real-time Bitstream Decompression Scheme for FPGAs Reconfiguration. MWSCAS Luka Daoud, Fady Hussein, Nader Rafla
2018	—	`conf`	Routing Aware and Runtime Detection for Infected Network-on-Chip Routers. MWSCAS Luka Daoud, Nader Rafla
2018	A	`conf`	SIFT Keypoint Descriptor Matching Algorithm: A Fully Pipelined Accelerator on FPGA(Abstract Only). FPGA Luka Daoud, Muhammad Kamran Latif, Nader Rafla
2017	—	`conf`	High level synthesis using vivado HLS for optimizations of SHA-3. MWSCAS H. S. Jacinto, Luka Daoud, Nader Rafla
2016	—	`conf`	Zynq-based SoC implementation of an induction machine control algorithm. MWSCAS Danyal Mohammadi, Luka Daoud, Nader Rafla, Said Ahmed-Zaid
2015	A	`conf`	Optimized Fixed-Point FPGA Implementation of SVPWM for a Two-Level Inverter (Abstract Only). FPGA Danyal Mohammadi, Said Ahmed-Zaid, Nader Rafla
2012	—	`conf`	Welcome to the 55 MWSCAS Nader Rafla, Mohamad Sawan, José M. de la Rosa