Nadav Rotem

18 papers B 1Misc 2Journal 13Unranked 2
YearRankTypeTitle / Venue / Authors
2025 J jnl
OpenZL: A Graph-Based Model for Compression.
CoRR
Yann Collet, Nick Terrell, W. Felix P. Handte, Danielle Rozenblit, Victor Zhang, Kevin Zhang, Yaelle Goldschlag, Jennifer Lee, Elliot Gorokhovsky, Yonatan Komornik, Daniel Riegel, Stan Angelov, Nadav Rotem
2021 J jnl
Profile Guided Optimization without Profiles: A Machine Learning Approach.
CoRR
Nadav Rotem, Chris Cummins
2020 J jnl
Warrior1: A Performance Sanitizer for C++.
CoRR
Nadav Rotem, Lee Howes, David Goldblatt
2018 J jnl
Deep Learning Inference in Facebook Data Centers: Characterization, Performance Optimizations and Hardware Implications.
CoRR
Jongsoo Park, Maxim Naumov, Protonu Basu, Summer Deng, Aravind Kalaiah, Daya Shanker Khudia, James Law, Parth Malani, Andrey Malevich, Nadathur Satish, Juan Miguel Pino, Martin Schatz, Alexander Sidorov, Viswanath Sivakumar, Andrew Tulloch, Xiaodong Wang, Yiming Wu, Hector Yuen, Utku Diril, Dmytro Dzhulgakov, Kim M. Hazelwood, Bill Jia, Yangqing Jia, Lin Qiao, Vijay Rao, Nadav Rotem, Sungjoo Yoo, Mikhail Smelyanskiy
2018 J jnl
Glow: Graph Lowering Compiler Techniques for Neural Networks.
CoRR
Nadav Rotem, Jordan Fix, Saleem Abdulrasool, Summer Deng, Roman Dzhabarov, James Hegeman, Roman Levenstein, Bert Maher, Nadathur Satish, Jakob Olesen, Jongsoo Park, Artem Rakhov, Misha Smelyanskiy
2014 J jnl
Block Unification IF-conversion for High Performance Architectures.
IEEE Comput. Archit. Lett.
Nadav Rotem, Yosi Ben-Asher
2013 J jnl
Hybrid type legalization for a sparse SIMD instruction set.
ACM Trans. Archit. Code Optim.
Yosi Ben-Asher, Nadav Rotem
2013 J jnl
Optimizing Wait States in the Synthesis of Memory References with Unpredictable Latencies.
ACM Trans. Reconfigurable Technol. Syst.
Yosi Ben-Asher, Ron Meldiner, Nadav Rotem
2013 J jnl
The benefits of using variable-length pipelined operations in high-level synthesis.
ACM Trans. Embed. Comput. Syst.
Yosi Ben-Asher, Nadav Rotem
2013 J jnl
Using memory profile analysis for automatic synthesis of pointers code.
ACM Trans. Embed. Comput. Syst.
Yosi Ben-Asher, Nadav Rotem
2011 J jnl
Combining static and dynamic array detection for binary synthesis with multiple memory ports.
Des. Autom. Embed. Syst.
Nadav Rotem, Yosi Ben-Asher
2011 — conf
Optimizing wait-states in the synthesis of memory references with unpredictable latencies.
ICSAMOS
Yosi Ben-Asher, Ron Meldiner, Nadav Rotem
2010 Misc conf
Automatic memory partitioning: increasing memory parallelism via data structure partitioning.
CODES+ISSS
Yosi Ben-Asher, Nadav Rotem
2010 J jnl
Finding the best compromise in compiling compound loops to Verilog.
J. Syst. Archit.
Yosi Ben-Asher, Nadav Rotem, Eddie Shochat
2010 J jnl
Reducing Memory Constraints in Modulo Scheduling Synthesis for FPGAs.
ACM Trans. Reconfigurable Technol. Syst.
Yosi Ben-Asher, Danny Meisler, Nadav Rotem
2009 B conf
Binary Synthesis with multiple memory banks targeting array references.
FPL
Yosi Ben-Asher, Nadav Rotem
2009 Misc conf
The effect of unrolling and inlining for Python bytecode optimizations.
SYSTOR
Yosi Ben-Asher, Nadav Rotem
2008 — conf
Synthesis for variable pipelined function units.
SoC
Yosi Ben-Asher, Nadav Rotem