Nacer-Eddine Zergainoh

69 papers A 8B 8C 14Journal 17Unranked 21

Year	Rank	Type	Title / Venue / Authors
2025	—	`conf`	Veritas-PUF: A Countermeasure against X-Ray Tampering and Side Channel Attacks. ATS Nasr-Eddine Ouldei Tebina, Luc Salvo, Marc Xander Makkes, Nacer-Eddine Zergainoh, Paolo Maistri
2024	A	`conf`	Enhancing Side-Channel Attacks Through X-Ray-Induced Leakage Amplification. DATE Nasr-Eddine Ouldei Tebina, Luc Salvo, Laurent Maingault, Nacer-Eddine Zergainoh, Guillaume Hubert, Paolo Maistri
2024	—	`conf`	Non-Invasive Attack on Ring Oscillator-Based PUFs Through Localized X-Ray Irradiation. HOST Nasr-Eddine Ouldei Tebina, Aghiles Douadi, Luc Salvo, Vincent Beroulle, Nacer-Eddine Zergainoh, Guillaume Hubert, Elena-Ioana Vatajelu, Giorgio Di Natale, Paolo Maistri
2023	C	`conf`	Ray-Spect: Local Parametric Degradation for Secure Designs: An application to X-Ray Fault Injection. IOLTS Nasr-Eddine Ouldei Tebina, Laurent Maingault, Nacer-Eddine Zergainoh, Guillaume Hubert, Paolo Maistri
2023	—	`conf`	Simulation Methodology for Assessing X-Ray Effects on Digital Circuits. DFT Nasr-Eddine Ouldei Tebina, Nacer-Eddine Zergainoh, Guillaume Hubert, Paolo Maistri
2022	—	`conf`	X-Ray Fault Injection: Reviewing Defensive Approaches from a Security Perspective. DFT Nasr-Eddine Ouldei Tebina, Nacer-Eddine Zergainoh, Paolo Maistri
2020	J	`jnl`	A Dynamic Sufficient Condition of Deadlock-Freedom for High-Performance Fault-Tolerant Routing in Networks-on-Chips. IEEE Trans. Emerg. Top. Comput. Amir Charif, Alexandre Coelho, Nacer-Eddine Zergainoh, Michael Nicolaidis
2019	—	`conf`	NoCFI: A Hybrid Fault Injection Method for Networks-On-Chip. LATS Alexandre Coelho, Nacer-Eddine Zergainoh, Raoul Velazco
2018	—	`conf`	A Runtime Fault-Tolerant Routing Scheme for Partially Connected 3D Networks-on-Chip. DFT Alexandre Coelho, Amir Charif, Nacer-Eddine Zergainoh, Raoul Velazco
2018	A	`conf`	A soft-error resilient route computation unit for 3D Networks-on-Chips. DATE Alexandre Coelho, Amir Charif, Nacer-Eddine Zergainoh, Juan A. Fraire, Raoul Velazco
2018	A	`conf`	Designing reliable processor cores in ultimate CMOS and beyond: A double sampling solution. DATE Thierry Bonnoit, Fraidy Bouesse, Nacer-Eddine Zergainoh, Michael Nicolaidis
2018	J	`jnl`	First-Last: A Cost-Effective Adaptive Routing Solution for TSV-Based Three-Dimensional Networks-on-Chip. IEEE Trans. Computers Amir Charif, Alexandre Coelho, Masoumeh Ebrahimi, Nader Bagherzadeh, Nacer-Eddine Zergainoh
2018	J	`jnl`	Reducing Rollback Cost in VLSI Circuits to Improve Fault Tolerance. IEEE Trans. Very Large Scale Integr. Syst. Thierry Bonnoit, Nacer-Eddine Zergainoh, Michael Nicolaidis
2017	J	`jnl`	A Framework for Scalable TSV Assignment and Selection in Three-Dimensional Networks-on-Chips. VLSI Design Amir Charif, Alexandre Coelho, Nacer-Eddine Zergainoh, Michael Nicolaidis
2017	J	`jnl`	Assessing Contact Graph Routing Performance and Reliability in Distributed Satellite Constellations. J. Comput. Networks Commun. Juan A. Fraire, Pablo G. Madoery, Scott C. Burleigh, Marius Feldmann, Jorge M. Finochietto, Amir Charif, Nacer-Eddine Zergainoh, Raoul Velazco
2017	—	`conf`	Detailed and highly parallelizable cycle-accurate network-on-chip simulation on GPGPU. ASP-DAC Amir Charif, Alexandre Coelho, Nacer-Eddine Zergainoh, Michael Nicolaidis
2017	—	`conf`	Low cost rollback to improve fault-tolerance in VLSI circuits. LASCAS Thierry Bonnoit, Nacer-Eddine Zergainoh, Michael Nicolaidis, Raoul Velazco
2017	—	`conf`	MINI-ESPADA: A low-cost fully adaptive routing mechanism for Networks-on-Chips. LATS Amir Charif, Alexandre Coelho, Nacer-Eddine Zergainoh, Michael Nicolaidis
2017	—	`conf`	Preliminary results of NETFI-2: An automatic method for fault injection on HDL-based designs. LATS M. Solinas, Alexandre Coelho, Juan A. Fraire, Nacer-Eddine Zergainoh, Pablo A. Ferreyra, Raoul Velazco
2017	B	`conf`	Rout3D: A lightweight adaptive routing algorithm for tolerating faulty vertical links in 3D-NoCs. ETS Amir Charif, Nacer-Eddine Zergainoh, Alexandre Coelho, Michael Nicolaidis
2017	—	`conf`	SEU impact in processor's control-unit: Preliminary results obtained for LEON3 soft-core. LATS Thierry Bonnoit, Alexandre Coelho, Nacer-Eddine Zergainoh, Raoul Velazco
2016	—	`conf`	A new approach to deadlock-free fully adaptive routing for high-performance fault-tolerant NoCs. DFT Amir Charif, Nacer-Eddine Zergainoh, Michael Nicolaidis
2016	B	`conf`	Addressing transient routing errors in fault-tolerant Networks-on-Chips. ETS Amir Charif, Nacer-Eddine Zergainoh, Michael Nicolaidis
2015	—	`conf`	Evaluating SEU fault-injection on parallel applications implemented on multicore processors. LASCAS Vanessa Vargas, Pablo Ramos, Raoul Velazco, Jean-François Méhaut, Nacer-Eddine Zergainoh
2015	C	`conf`	MUGEN: A high-performance fault-tolerant routing algorithm for unreliable Networks-on-Chip. IOLTS Amir Charif, Nacer-Eddine Zergainoh, Michael Nicolaidis
2014	B	`conf`	A generic and high-level model of large unreliable NoCs for fault tolerance and performance analysis. ETS Fabien Chaix, Nacer-Eddine Zergainoh, Michael Nicolaidis
2014	J	`jnl`	Fault-tolerant adaptive routing under an unconstrained set of node and link failures for many-core systems-on-chip. Microprocess. Microsystems Michael G. Dimopoulos, Yi Gang, Lorena Anghel, Mounir Benabdenbi, Nacer-Eddine Zergainoh, Michael Nicolaidis
2014	C	`conf`	Preliminary results of SEU fault-injection on multicore processors in AMP mode. IOLTS Vanessa Vargas, Pablo Ramos, Wassim Mansour, Raoul Velazco, Nacer-Eddine Zergainoh, Jean-François Méhaut
2013	C	`conf`	Fault-tolerant adaptive routing under permanent and temporary failures for many-core systems-on-chip. IOLTS Michael G. Dimopoulos, Yi Gang, Mounir Benabdenbi, Lorena Anghel, Nacer-Eddine Zergainoh, Michael Nicolaidis
2013	J	`jnl`	Using Error Correcting Codes Without Speed Penalty in Embedded Memories: Algorithm, Implementation and Case Study. J. Electron. Test. Thierry Bonnoit, Michael Nicolaidis, Nacer-Eddine Zergainoh
2013	B	`conf`	Variability-aware and fault-tolerant self-adaptive applications for many-core chips. ETS Gilles Bizot, Fabien Chaix, Nacer-Eddine Zergainoh, Michael Nicolaidis
2013	C	`conf`	Variability-aware and fault-tolerant self-adaptive applications for many-core chips. IOLTS Gilles Bizot, Fabien Chaix, Nacer-Eddine Zergainoh, Michael Nicolaidis
2012	A	`conf`	Design for test and reliability in ultimate CMOS. DATE Michael Nicolaidis, Lorena Anghel, Nacer-Eddine Zergainoh, Yervant Zorian, Tanay Karnik, Keith A. Bowman, James W. Tschanz, Shih-Lien Lu, Carlos Tokunaga, Arijit Raychowdhury, Muhammad M. Khellah, Jaydeep P. Kulkarni, Vivek De, Dimiter Avresky
2011	A	`conf`	A fault-tolerant deadlock-free adaptive routing for on chip interconnects. DATE Fabien Chaix, Dimiter Avresky, Nacer-Eddine Zergainoh, Michael Nicolaidis
2011	B	`conf`	Efficient Fault Detection Architecture Design of Latch-Based Low Power DSP/MCU Processor. ETS Hai Yu, Michael Nicolaidis, Lorena Anghel, Nacer-Eddine Zergainoh
2011	A	`conf`	Eliminating speed penalty in ECC protected memories. DATE Michael Nicolaidis, Thierry Bonnoit, Nacer-Eddine Zergainoh
2011	J	`jnl`	On-line Power Optimization of Data Flow Multi-Core Architecture Based on Vdd-Hopping for Local Dynamic Voltage and Frequency Scaling. J. Low Power Electron. Pascal Vivet, Edith Beigné, Hugo Lebreton, Nacer-Eddine Zergainoh
2011	B	`conf`	Self-Recovering Parallel Applications in Multi-core Systems. NCA Gilles Bizot, Dimiter Avresky, Fabien Chaix, Nacer-Eddine Zergainoh, Michael Nicolaidis
2011	C	`conf`	Towards a tool for implementing delay-free ECC in embedded memories. ICCD Thierry Bonnoit, Michael Nicolaidis, Nacer-Eddine Zergainoh
2011	C	`conf`	Variability-aware task mapping strategies for many-cores processor chips. IOLTS Fabien Chaix, Gilles Bizot, Michael Nicolaidis, Nacer-Eddine Zergainoh
2010	B	`conf`	Fault-Tolerant Deadlock-Free Adaptive Routing for Any Set of Link and Node Failures in Multi-cores Systems. NCA Fabien Chaix, Dimiter Avresky, Nacer-Eddine Zergainoh, Michael Nicolaidis
2010	—	`conf`	On Line Power Optimization of Data Flow Multi-core Architecture Based on Vdd-Hopping for Local DVFS. PATMOS Pascal Vivet, Edith Beigné, Hugo Lebreton, Nacer-Eddine Zergainoh
2009	C	`conf`	Variability and reliability-aware application tasks scheduling and power control (Voltage and Frequency Scaling) in the future nanoscale multiprocessors system on chip. IOLTS Gilles Bizot, Nacer-Eddine Zergainoh, Michael Nicolaidis
2007	B	`conf`	Buffer Size Reduction through Control-Flow Decomposition. RTCSA Youngchul Cho, Nacer-Eddine Zergainoh, Ahmed Amine Jerraya, Kiyoung Choi
2007	C	`conf`	Low Runtime-Overhead Software Synthesis for Communicating Concurrent Processes. IEEE International Workshop on Rapid System Prototyping Youngchul Cho, Nacer-Eddine Zergainoh, Kiyoung Choi, Ahmed Amine Jerraya
2007	J	`jnl`	Scheduling with accurate communication delay model and scheduler implementation for multiprocessor system-on-chip. Des. Autom. Embed. Syst. Youngchul Cho, Nacer-Eddine Zergainoh, Sungjoo Yoo, Ahmed Amine Jerraya, Kiyoung Choi
2007	—	`conf`	Simulink-based MPSoC Design: New Approach to Bridge the Gap between Algorithm and Architecture Design. ISVLSI Youssef Atat, Nacer-Eddine Zergainoh
2006	J	`jnl`	Automatic delay correction method for IP block-based design of VLSI dedicated digital signal processing systems: theoretical foundations and implementation. IEEE Trans. Very Large Scale Integr. Syst. Nacer-Eddine Zergainoh, Ludovic Tambour, Ahmed Amine Jerraya
2006	J	`jnl`	Macrocell Builder: IP-Block-Based Design Environment for High-Throughput VLSI Dedicated Digital Signal Processing Systems. EURASIP J. Adv. Signal Process. Nacer-Eddine Zergainoh, Ludovic Tambour, Pascal Urard, Ahmed Amine Jerraya
2005	J	`jnl`	Hardware/software codesign of on-chip communication architecture for application-specific multiprocessor system-on-chip. Int. J. Embed. Syst. Nacer-Eddine Zergainoh, Amer Baghdadi, Ahmed Amine Jerraya
2005	—	`conf`	IP-block-based design environment for high-throughput VLSI dedicated digital signal processing systems. ASP-DAC Nacer-Eddine Zergainoh, Katalin Popovici, Ahmed Amine Jerraya, Pascal Urard
2005	J	`jnl`	Méthodes de correction de retard dans les modèles RTL des systèmes monopuces DSP obtenus par assemblage de composants IP : fondement théorique et implémentation. Tech. Sci. Informatiques Nacer-Eddine Zergainoh, Ludovic Tambour, Henri Michel, Ahmed Amine Jerraya
2005	—	`conf`	Scheduler implementation in MP SoC design. ASP-DAC Youngchul Cho, Sungjoo Yoo, Kiyoung Choi, Nacer-Eddine Zergainoh, Ahmed Amine Jerraya
2004	J	`jnl`	A generic architecture model based-methodology for an efficient design of hardware/software application-specific multiprocessor System-on-Chip. Ann. des Télécommunications Nacer-Eddine Zergainoh, Amer Baghdadi, Ahmed Amine Jerraya
2003	C	`conf`	An Efficient Methodology and Semi-Automated Flow for Design and Validation of Complex Digital Signal Processing ASICS Macro-Cells. IEEE International Workshop on Rapid System Prototyping Ludovic Tambour, Nacer-Eddine Zergainoh, Pascal Urard, Henri Michel, Ahmed Amine Jerraya
2003	—	`ch.`	Scheduling and Timing Analysis of HW/SW On-Chip Communication in MP SoC Design. Embedded Software for SoC Youngchul Cho, Ganghee Lee, Kiyoung Choi, Sungjoo Yoo, Nacer-Eddine Zergainoh
2003	A	`conf`	Scheduling and Timing Analysis of HW/SW On-Chip Communication in MP SoC Design. DATE Youngchul Cho, Ganghee Lee, Sungjoo Yoo, Kiyoung Choi, Nacer-Eddine Zergainoh
2002	J	`jnl`	Combining a Performance Estimation Methodology with a Hardware/Software Codesign Flow Supporting Multiprocessor Systems. IEEE Trans. Software Eng. Amer Baghdadi, Nacer-Eddine Zergainoh, Wander O. Cesário, Ahmed Amine Jerraya
2002	J	`jnl`	Exploration de l'espace des solutions architecturales dans le codesign. Tech. Sci. Informatiques Amer Baghdadi, Nacer-Eddine Zergainoh, Wander O. Cesário, Ahmed Amine Jerraya
2001	A	`conf`	An efficient architecture model for systematic design of application-specific multiprocessor SoC. DATE Amer Baghdadi, Damien Lyonnard, Nacer-Eddine Zergainoh, Ahmed Amine Jerraya
2000	C	`conf`	Design Space Exploration for Hardware/Software Codesign of Multiprocessor Systems. IEEE International Workshop on Rapid System Prototyping Amer Baghdadi, Nacer-Eddine Zergainoh, Wander O. Cesário, T. Roudier, Ahmed Amine Jerraya
2000	—	`conf`	Framework for System Design, Validation and Fast Prototyping of Multiprocessor System-On-Chip. DIPES Nacer-Eddine Zergainoh, Amer Baghdadi, Ludovic Tambour, Damien Lyonnard, Lovic Gauthier, Ahmed Amine Jerraya
2000	—	`conf`	Generic Architecture Platform for Multiprocessor System-On-Chip Design. DIPES Amer Baghdadi, Nacer-Eddine Zergainoh, Damien Lyonnard, Ahmed Amine Jerraya
2000	J	`jnl`	Interlanguage Communication Synthesis for Heterogeneous Specifications. Des. Autom. Embed. Syst. Fabiano Hessel, Pascal Coste, Philippe Le Marrec, Nacer-Eddine Zergainoh, Gabriela Nicolescu, Jean-Marc Daveau, Ahmed Amine Jerraya
2000	C	`conf`	Multi-Level Communication Synthesis of Heterogeneous Multilanguage Specification. ICCD Fabiano Hessel, Philippe Coste, Gabriela Nicolescu, P. LeMarrec, Nacer-Eddine Zergainoh, Ahmed Amine Jerraya
2000	—	`conf`	Towards design and validation of mixed-technology SOCs. ACM Great Lakes Symposium on VLSI Salvador Mir, Benoît Charlot, Gabriela Nicolescu, Philippe Coste, Fabien Parrain, Nacer-Eddine Zergainoh, Bernard Courtois, Ahmed Amine Jerraya, Márta Rencz
1999	C	`conf`	Communication Interface Synthesis for Multilanguage Specifications. IEEE International Workshop on Rapid System Prototyping Fabiano Hessel, Philippe Coste, P. LeMarrec, Nacer-Eddine Zergainoh, Jean-Marc Daveau, Ahmed Amine Jerraya
1999	—	`conf`	Multilanguage design of heterogeneous systems. CODES Philippe Coste, Fabiano Hessel, P. LeMarrec, Zoltan Sugar, Mohamed Romdhani, Rodolph Suescun, Nacer-Eddine Zergainoh, Ahmed Amine Jerraya
1994	C	`conf`	A Real Time Multiprocessor Application Development Environment Design And Implementation. PDP Nacer-Eddine Zergainoh, Thierry Maurin, Yves Sorel, Christophe Lavarenne