N. S. Nagaraj

28 papers A* 7C 2Misc 8Journal 1Unranked 10
YearRankTypeTitle / Venue / Authors
2009 A* conf
Moore's Law: another casualty of the financial meltdown?
DAC
Jason Cong, N. S. Nagaraj, Ruchir Puri, William H. Joyner, Jeff Burns, Moshe Gavrielov, Riko Radojcic, Peter Rickert, Hans Stork
2008 A* conf
DFM in practice: hit or hype?
DAC
Juan C. Rey, N. S. Nagaraj, Andrew B. Kahng, Fabian Klass, Rob Aitken, Cliff Hou, Luigi Capodieci, Vivek Singh
2006 Misc conf
Interconnect Process Variations: Theory and Practice.
VLSI Design
N. S. Nagaraj
2006 — conf
Optimizing Interconnect for Performance in Standard Cell Library.
APCCAS
Dharin Shah, Kothamasu Siva, G. Girishankar, N. S. Nagaraj
2006 Misc conf
SmartExtract: Accurate Capacitance Extraction for SOC Designs.
VLSI Design
Usha Narasimha, Anthony M. Hill, N. S. Nagaraj
2006 — conf
Statistical Analysis of Capacitance Coupling Effects on Delay and Noise.
ISQED
Usha Narasimha, Binu Abraham, N. S. Nagaraj
2005 A* conf
BEOL variability and impact on RC extraction.
DAC
N. S. Nagaraj, Tom Bonifield, Abha Singh, Clive Bittlestone, Usha Narasimha, Viet Le, Anthony M. Hill
2005 — conf
Dealing with interconnect process variations.
SLIP
N. S. Nagaraj
2005 Misc conf
The Impact of Inductance on Transients Affecting Gate Oxide Reliability.
VLSI Design
N. S. Nagaraj, William R. Hunter, Poras T. Balsara, Cyrus D. Cantrell
2004 Misc conf
A 800 MHz System-on-Chip for Wireless Infrastructure Applications.
VLSI Design
Sanjive Agarwala, Paul Wiley, Arjun Rajagopal, Anthony M. Hill, Raguram Damodaran, Lewis Nardini, Tim Anderson, Steven Mullinnix, Jose Flores, Heping Yue, Abhijeet Chachad, John Apostol, Kyle Castille, Usha Narasimha, Tod Wolf, N. S. Nagaraj, Manjeri Krishnan, Luong Nguyen, Todd Kroeger, Mike Gill, Peter Groves, Bill Webster, Joel Graber, Christine Karlovich
2004 — conf
Autonomic Incident Manager for Enterprise Applications.
GCC Workshops
Renuka Sindhgatta, Swaminathan Natarajan, Krishnakumar Pooloth, Colin Pinto, N. S. Nagaraj
2004 Misc conf
Interconnect Modeling for Copper/Low-k Technologies.
VLSI Design
N. S. Nagaraj, Tom Bonifield, Abha Singh, Roger Griesmer, Poras T. Balsara
2003 — conf
Benchmarks for Interconnect Parasitic Resistance and Capacitance.
ISQED
N. S. Nagaraj, Tom Bonifield, Abha Singh, Frank Cano, Usha Narasimha, Mak Kulkarni, Poras T. Balsara, Cyrus D. Cantrell
2002 J jnl
A 600-MHz VLIW DSP.
IEEE J. Solid State Circuits
Sanjive Agarwala, Timothy Anderson, Anthony M. Hill, M. D. Ales, Raguram Damodaran, Paul Wiley, Steven Mullinnix, J. Leach, Anthony Lell, Michael Gill, Arjun Rajagopal, Abhijeet Chachad, M. Agarwala, John Apostol, Manjeri Krishnan, Duc Bui, Quang An, N. S. Nagaraj, Tod Wolf, T. T. Elappuparackal
2002 — conf
Embedded Tutorial: Modeling Parasitic Coupling Effects in Reliability Verification.
ASP-DAC/VLSI Design
N. S. Nagaraj, Poras T. Balsara, Cyrus D. Cantrell
2001 — conf
Interconnect Modeling for Timing, Signal Integrity and Reliability.
ISQED
Narain Arora, N. S. Nagaraj
2000 Misc conf
A Practical Approach to Crosstalk Noise Verification of Static CMOS Designs.
VLSI Design
N. S. Nagaraj, Frank Cano, Duane Young, Deepak Vohra, Manoj Das
2000 — conf
Enabling DIR(Designing-In-Reliability) through CAD Capabilities.
ISQED
Wonjae L. Kang, Brad Potts, Ray Hokinson, John Riley, David Doman, Frank Cano, N. S. Nagaraj, Noel Durrant
2000 — conf
Full-Chip Signal Interconnect Analysis for Electromigration Reliability.
ISQED
Steffen Rochel, N. S. Nagaraj
2000 A* conf
When bad things happen to good chips (panel session).
DAC
N. S. Nagaraj, Andrzej J. Strojwas, Sani R. Nassif, Ray Hokinson, Tak Young, Wonjae L. Kang, David Overhauser, Sung-Mo Kang
1998 A* conf
A Practical Approach to Static Signal Electromigration Analysis.
DAC
N. S. Nagaraj, Frank Cano, Haldun Haznedar, Duane Young
1998 A* conf
Taming Noise in Deep Submicron Digital Integrated Circuits (Panel).
DAC
N. S. Nagaraj, Kenneth L. Shepard, Takahide Inone
1997 — conf
Chip hierarchical design system (CHDS): a foundation for timing-driven physical design into the 21st century.
ISPD
R. G. Bushroe, S. Dasgupta, A. Dengi, P. Fisher, S. Grout, G. Ledenbach, N. S. Nagaraj, R. Steele
1994 C conf
Approximate Computation of Signal Characteristics of On-chip RC Interconnect Trees.
ISCAS
N. S. Nagaraj, Paul Krivacek, Mark Harward
1993 A* conf
A New Optimizer for Performance Optimization of Analog Integrated Circuits.
DAC
N. S. Nagaraj
1993 C conf
A New Optimizer for Performance Optimization of Integrated Circuits by Device Sizing.
ISCAS
N. S. Nagaraj
1992 Misc conf
OPSYN - OASYS Based Pseudosynthesis Tool.
VLSI Design
N. S. Nagaraj
1992 Misc conf
WCS - A CAD Solution for Worst Case Performance Analysis of Integrated Circuits.
VLSI Design
S. Nagaraj, N. Padmini, N. S. Nagaraj, R. Ramesh, V. Sachidanand