N. Ranganathan

150 papers A* 4A 7B 8C 17Misc 26Journal 47Unranked 41
YearRankTypeTitle / Venue / Authors
2011 A conf
A new reversible design of BCD adder.
DATE
Himanshu Thapliyal, N. Ranganathan
2011 C conf
An Instruction-Level Energy Estimation and Optimization Methodology for GPU.
CIT
Yue Wang, N. Ranganathan
2011 J jnl
Placement for Immunity of Transient Faults in Cell-Based Design of Nanometer Circuits.
IEEE Trans. Very Large Scale Integr. Syst.
Koustav Bhattacharya, N. Ranganathan
2010 J jnl
A VLSI Architecture and Algorithm for Lucas-Kanade-Based Optical Flow Computation.
IEEE Trans. Very Large Scale Integr. Syst.
Venkataraman Mahalingam, Koustav Bhattacharya, N. Ranganathan, Hari Chakravarthula, Robin R. Murphy, Kevin S. Pratt
2010 J jnl
Timing-Based Placement Considering Uncertainty Due to Process Variations.
IEEE Trans. Very Large Scale Integr. Syst.
Venkataraman Mahalingam, N. Ranganathan
2009 C conf
A Strategy for Soft Error Reduction in Multi Core Designs.
ISCAS
Ransford Hyman Jr., Koustav Bhattacharya, N. Ranganathan
2008 J jnl
A Fuzzy Optimization Approach for Variation Aware Power Minimization During Gate Sizing.
IEEE Trans. Very Large Scale Integr. Syst.
Venkataraman Mahalingam, N. Ranganathan, J. E. Harlow
2008 — conf
Simultaneous optimization of total power, crosstalk noise, and delay under uncertainty.
ACM Great Lakes Symposium on VLSI
N. Ranganathan, Upavan Gupta, Venkataraman Mahalingam
2007 — conf
Variation Aware Timing Based Placement Using Fuzzy Programming.
ISQED
Venkataraman Mahalingam, N. Ranganathan
2006 A conf
A novel approach for variation aware power minimization during gate sizing.
ISLPED
Venkataraman Mahalingam, N. Ranganathan, Justin E. Harlow III
2006 J jnl
A stimulus-free graphical probabilistic switching model for sequential circuits using dynamic bayesian networks.
ACM Trans. Design Autom. Electr. Syst.
Sanjukta Bhanja, Karthikeyan Lingasubramanian, N. Ranganathan
2006 Misc conf
An Efficient and Accurate Logarithmic Multiplier Based on Operand Decomposition.
VLSI Design
Venkataraman Mahalingam, N. Ranganathan
2006 J jnl
ILP models for simultaneous energy and transient power minimization during behavioral synthesis.
ACM Trans. Design Autom. Electr. Syst.
Saraju P. Mohanty, N. Ranganathan, Sunil K. Chappidi
2006 C conf
Social Fairness in Multi-Emergency Resource Management.
ISTAS
Upavan Gupta, N. Ranganathan
2005 — conf
A Nonlinear Programming Based Power Optimization Methodology for Gate Sizing and Voltage Selection.
ISVLSI
Venkataraman Mahalingam, N. Ranganathan
2005 Misc conf
Design of a Low Power Image Watermarking Encoder Using Dual Voltage and Frequency.
VLSI Design
Saraju P. Mohanty, N. Ranganathan, Karthikeyan Balakrishnan
2005 J jnl
Energy-efficient datapath scheduling using multiple voltages and dynamic clocking.
ACM Trans. Design Autom. Electr. Syst.
Saraju P. Mohanty, N. Ranganathan
2005 Misc conf
Estimation of Switching Activity in Sequential Circuits Using Dynamic Bayesian Networks.
VLSI Design
Sanjukta Bhanja, Karthikeyan Lingasubramanian, N. Ranganathan
2004 J jnl
Cascaded Bayesian inferencing for switching activity estimation with correlated inputs.
IEEE Trans. Very Large Scale Integr. Syst.
Sanjukta Bhanja, N. Ranganathan
2004 J jnl
Editorial.
IEEE Trans. Very Large Scale Integr. Syst.
N. Ranganathan
2004 Misc conf
Game Theoretic Modeling of Voltage and Frequency Scaling during Behavioral Synthesis.
VLSI Design
Ashok K. Murugavel, N. Ranganathan
2004 Misc conf
Gate Sizing and Buffer Insertion using Economic Models for Power Optimization.
VLSI Design
Ashok K. Murugavel, N. Ranganathan
2004 J jnl
Stochastic channel-adaptive rate control for wireless video transmission.
Pattern Recognit. Lett.
Ramamurti Chandramouli, Koduvayur P. Subbalakshmi, N. Ranganathan
2003 Misc conf
A Framework for Energy and Transient Power Reduction during Behavioral Synthesis.
VLSI Design
Saraju P. Mohanty, N. Ranganathan
2003 Misc conf
A Game-Theoretic Approach for Binding in Behavioral Synthesis.
VLSI Design
Ashok K. Murugavel, N. Ranganathan
2003 C conf
A Microeconomic Model for Simultaneous Gate Sizing and Voltage Scaling for Power Optimization.
ICCD
N. Ranganathan, Ashok K. Murugavel
2003 J jnl
A game theoretic approach for power optimization during behavioral synthesis.
IEEE Trans. Very Large Scale Integr. Syst.
Ashok K. Murugavel, N. Ranganathan
2003 Misc conf
A low power scheduler using game theory.
CODES+ISSS
N. Ranganathan, Ashok K. Murugavel
2003 — conf
An ILP-based scheduling scheme for energy efficient high performance datapath synthesis.
ISCAS (5)
Saraju P. Mohanty, N. Ranganathan, Sunil K. Chappidi
2003 Misc conf
Energy Efficient Scheduling for Datapath Synthesis.
VLSI Design
Saraju P. Mohanty, N. Ranganathan
2003 J jnl
Multiterminal net routing for partial crossbar-based multi-FPGA systems.
IEEE Trans. Very Large Scale Integr. Syst.
Abdel Ejnioui, N. Ranganathan
2003 — conf
Peak Power Minimization Through Datapath Scheduling.
ISVLSI
Saraju P. Mohanty, N. Ranganathan, Sunil K. Chappidi
2003 J jnl
Petri net modeling of gate and interconnect delays for power estimation.
IEEE Trans. Very Large Scale Integr. Syst.
Ashok K. Murugavel, N. Ranganathan
2003 C conf
Power Fluctuation Minimization During Behavioral Synthesis using ILP-Based Datapath Scheduling.
ICCD
Saraju P. Mohanty, N. Ranganathan, Sunil K. Chappidi
2003 J jnl
Routing on field-programmable switch matrices.
IEEE Trans. Very Large Scale Integr. Syst.
Abdel Ejnioui, N. Ranganathan
2003 — conf
Simultaneous peak and average power minimization during datapath scheduling for DSP processors.
ACM Great Lakes Symposium on VLSI
Saraju P. Mohanty, N. Ranganathan, Sunil K. Chappidi
2003 J jnl
Switching activity estimation of VLSI circuits using Bayesian networks.
IEEE Trans. Very Large Scale Integr. Syst.
Sanjukta Bhanja, N. Ranganathan
2002 — conf
A Real Delay Switching Activity Simulator Based on Petri Net Modeling.
ASP-DAC/VLSI Design
Ashok K. Murugavel, N. Ranganathan
2002 — conf
A VLSI Architecture for Object Recognition Using Tree Matching.
ASAP
K. Sitaraman, N. Ranganathan, Abdel Ejnioui
2002 J jnl
A comparative study of bidirectional ring and crossbar interconnection networks.
Comput. Electr. Eng.
Hitoshi Oi, N. Ranganathan
2002 — conf
Datapath Scheduling using Dynamic Frequency Clocking.
ISVLSI
Saraju P. Mohanty, N. Ranganathan, Vamsi Krishna
2002 J jnl
Least-square estimation of average power in digital CMOS circuits.
IEEE Trans. Very Large Scale Integr. Syst.
Ashok K. Murugavel, N. Ranganathan, Ramamurti Chandramouli, Srinath Chavali
2002 C conf
Modeling Switching Activity Using Cascaded Bayesian Networks for Correlated Input Streams.
ICCD
Sanjukta Bhanja, N. Ranganathan
2002 A* conf
Petri net modeling of gate and interconnect delays for power estimation.
DAC
Ashok K. Murugavel, N. Ranganathan
2002 A conf
Power estimation of sequential circuits using hierarchical colored hardware petri net modeling.
ISLPED
Ashok K. Murugavel, N. Ranganathan
2002 — conf
Switching Activity Estimation of Large Circuits using Multiple Bayesian Networks.
ASP-DAC/VLSI Design
Sanjukta Bhanja, N. Ranganathan
2001 J jnl
A partitioning algorithm for technoiogy-mapped designs on single-chip emulation systems.
IEEE Trans. Very Large Scale Integr. Syst.
Abdel Ejnioui, N. Ranganathan
2001 J jnl
An intelligent system for failure detection and control in an autonomous underwater vehicle.
IEEE Trans. Syst. Man Cybern. Part A
N. Ranganathan, Minesh I. Patel, R. Sathyamurthy
2001 Misc conf
Average Power in Digital CMOS Circuits using Least Square Estimation.
VLSI Design
Ashok K. Murugavel, N. Ranganathan, Ramamurti Chandramouli, Srinath Chavali
2001 J jnl
Context-based lossless image coding using EZW framework.
IEEE Trans. Circuits Syst. Video Technol.
Veeru N. Ramaswamy, Kameswara Rao Namuduri, N. Ranganathan
2001 A* conf
Dependency Preserving Probabilistic Modeling of Switching Activity using Bayesian Networks.
DAC
Sanjukta Bhanja, N. Ranganathan
2001 J jnl
IDUTC: an intelligent decision-making system for urban traffic-control applications.
IEEE Trans. Veh. Technol.
Minesh I. Patel, N. Ranganathan
2000 Misc conf
CREAM: Combined Register and Module Assignment with Floorplanning for Low Power Datapath Synthesis.
VLSI Design
Vamsi K. Srikantam, N. Ranganathan, Srikanth Srinivasan
2000 Misc conf
Design Partitioning on Single-Chip Emulation Systems.
VLSI Design
Abdel Ejnioui, N. Ranganathan
2000 — conf
New Cost Metrics for Iterative Task Assignment Algorithms in Heterogeneous Computing Systems.
Heterogeneous Computing Workshop
Raju D. Venkataramana, N. Ranganathan
2000 Misc conf
Routing on Switch Matrix Multi-FPGA Systems.
VLSI Design
Abdel Ejnioui, N. Ranganathan
2000 J jnl
Utilization of cache area in on-chip multiprocessor.
Microprocess. Microsystems
Hitoshi Oi, N. Ranganathan
1999 Misc conf
A Learning Automata Based Framework for Task Assignment in Heterogeneous Computing Systems.
SAC
Raju D. Venkataramana, N. Ranganathan
1999 J jnl
A tree-matching chip.
IEEE Trans. Very Large Scale Integr. Syst.
Vamsi Krishna, N. Ranganathan, Abdel Ejnioui
1999 J jnl
Computation of lower bounds for switching activity using decision theory.
IEEE Trans. Very Large Scale Integr. Syst.
Vamsi Krishna, Ramamurti Chandramouli, N. Ranganathan
1999 J jnl
Computing the bivariate Gaussian probability integral.
IEEE Signal Process. Lett.
Ramamurti Chandramouli, N. Ranganathan
1999 — conf
Context based lossless intraframe coding of video sequence using embedded zerotree wavelets.
ISCAS (4)
Veeru N. Ramaswamy, Kameswara Rao Namuduri, N. Ranganathan
1999 Misc conf
Energy Efficient Datapath Synthesis Using Dynamic Frequency Clocking and Multiple Voltages.
VLSI Design
Vamsi Krishna, N. Ranganathan, Narayanan Vijaykrishnan
1999 A conf
Multi-Terminal Net Routing for Partial Crossbar-Based Multi-FPGA Systems.
FPGA
Abdel Ejnioui, N. Ranganathan
1999 — conf
Multiple Cost Optimization for Task Assignment in Heterogeneous Computing Systems Using Learning Automata.
Heterogeneous Computing Workshop
Raju D. Venkataramana, N. Ranganathan
1999 J jnl
Performance analysis of wavelets in embedded zerotree-based lossless image coding schemes.
IEEE Trans. Signal Process.
Veeru N. Ramaswamy, N. Ranganathan, Kameswara Rao Namuduri
1999 — conf
Tuning Branch Predictors to Support Virtual Method Invocation in Java.
COOTS
Narayanan Vijaykrishnan, N. Ranganathan
1999 — conf
Utilization of Cache Area in On-Chip Multiprocessor.
ISHPC
Hitoshi Oi, N. Ranganathan
1998 J jnl
A Forum for VLSI Practitioners.
Computer
N. Ranganathan
1998 — conf
A Methodology for High Level Power Estimation and Exploration.
Great Lakes Symposium on VLSI
Vamsi Krishna, N. Ranganathan
1998 J jnl
A VLSI Architecture for Approximate Tree Matching.
IEEE Trans. Computers
Raghu Sastry, N. Ranganathan
1998 J jnl
A generalized sequential sign detector for binary hypothesis testing.
IEEE Signal Process. Lett.
Ramamurti Chandramouli, N. Ranganathan
1998 — conf
A scene-based generalized Markov chain model for VBR video traffic.
ICC
Girish Chiruvolu, Tapas K. Das, Ravi Sankar, N. Ranganathan
1998 C conf
A simple adaptive wormhole routing algorithm for MIMD systems.
ICCD
Raju D. Venkataramana, N. Ranganathan
1998 J jnl
Adaptive VBR video traffic management for higher utilization of ATM networks.
Comput. Commun. Rev.
Girish Chiruvolu, Ravi Sankar, N. Ranganathan
1998 J jnl
Adaptive quantization and fast error-resilient entropy coding for image transmission.
IEEE Trans. Circuits Syst. Video Technol.
Ramamurti Chandramouli, N. Ranganathan, Shivaraman J. Ramadoss
1998 Misc conf
Computation of Lower and Upper Bounds for Switching Activity: A Unified Approach.
VLSI Design
Vamsi Krishna, Ramamurti Chandramouli, N. Ranganathan
1998 B conf
Empirical Channel Matched Quantizer Design and UEP for Robust Image Transmission.
Data Compression Conference
Ramamurti Chandramouli, N. Ranganathan, Shivaraman J. Ramadoss
1998 — conf
Joint Optimization of Quantization and On-Line Channel Estimation for Low Bit-Rate Video Transmission.
ICIP (1)
Ramamurti Chandramouli, Sharad Kumar, N. Ranganathan
1998 A conf
Object-Oriented Architectural Support for a Java Processor.
ECOOP
Narayanan Vijaykrishnan, N. Ranganathan, Ravi Gadekarla
1998 B conf
Rate control for a video coder using learning automata.
SMC
Ramamurti Chandramouli, Sharad Kumar, N. Ranganathan
1998 J jnl
SMAC: A VLSI Architecture for Scene Matching.
Real Time Imaging
N. Ranganathan, Raghu Sastry, Raguveer Venkatesan
1997 Misc conf
C3L: A Chip for Connected Component Labeling.
VLSI Design
Ashley Rasquinha, N. Ranganathan
1997 C conf
Effect of Message Length and Processor Speed on the Performance of the Bidirectional Ring-Based Multiprocessor.
ICCD
Hitoshi Oi, N. Ranganathan
1997 — conf
Performance Analysis of Wavelets in Embedded Zerotree-Based Lossless Image Coding Schemes.
ICIP (2)
Veeru N. Ramaswamy, Kameswara Rao Namuduri, N. Ranganathan
1996 — conf
A VLSI System Architecture For Real-Time Intelligent Decision Making.
ASAP
Minesh I. Patel, N. Ranganathan
1996 C conf
A VLSI array architecture with dynamic frequency clocking.
ICCD
N. Ranganathan, Narayanan Vijaykrishnan, N. Bhavanishankar
1996 C conf
A VLSI chip for image compression using variable block size segmentation.
ICCD
S. B. Aruru, N. Ranganathan, Kameswara Rao Namuduri
1996 B conf
A VLSI system architecture for lossless image compression.
ICPR
S. B. Aruru, N. Ranganathan, Kameswara Rao Namuduri
1996 B conf
A dynamic frequency linear array processor for image processing.
ICPR
N. Ranganathan, N. Bhavanishankar, Narayanan Vijaykrishnan
1996 Misc conf
A tree matching chip.
VLSI Design
Vamsi Krishna, Abdel Ejnioui, N. Ranganathan
1996 — conf
An intelligent system architecture for urban traffic control applications.
SPDP
Minesh I. Patel, N. Ranganathan
1996 B conf
Lossless image compression using wavelet decomposition.
ICPR
Veeru N. Ramaswamy, Kameswara Rao Namuduri, N. Ranganathan
1996 — conf
Mapping and parallel implementation of Bayesian belief networks.
SPDP
Nina Saxena, Sudeep Sarkar, N. Ranganathan
1996 — conf
PANTHER: a parallel neuro-systolic architecture for real-time processing.
ICNN
Minesh I. Patel, N. Ranganathan
1996 B conf
SIMD algorithms for single link and complete link pattern clustering.
ICPR
S. Arumugavelu, N. Ranganathan
1996 Misc conf
SUBGEN: a genetic approach for subcircuit extraction.
VLSI Design
Narayanan Vijaykrishnan, N. Ranganathan
1996 B conf
SVBS: a high-resolution medical image compression algorithm using slicing with variable block size segmentation.
ICPR
Kameswara Rao Namuduri, N. Ranganathan, Hooman Rashedi
1995 A* conf
A VLSI Architecture for Computer the Tree-to-Tree Distance.
HPCA
Raghu Sastry, N. Ranganathan
1995 — conf
A prototype VLSI chip architecture for JPEG image compression.
ED&TC
Mario Kovac, N. Ranganathan, Martin Zagar
1995 — conf
A systolic algorithm and architecture for image thinning.
Great Lakes Symposium on VLSI
N. Ranganathan, K. B. Doreswamy
1995 J jnl
CASM: A VLSI Chip for Approximate String Matching.
IEEE Trans. Pattern Anal. Mach. Intell.
Raghu Sastry, N. Ranganathan, Klinton Remedios
1995 J jnl
Conference Reports.
IEEE Des. Test Comput.
N. Ranganathan, Sharad C. Seth
1995 J jnl
JAGUAR: a fully pipelined VLSI architecture for JPEG image compression standard.
Proc. IEEE
Mario Kovac, N. Ranganathan
1995 Misc conf
JAGUAR: a high speed VLSI chip for JPEG image compression standard.
VLSI Design
Mario Kovac, N. Ranganathan
1995 J jnl
PMAC: A Polygon Matching Chip.
Int. J. Pattern Recognit. Artif. Intell.
Raghu Sastry, N. Ranganathan
1995 C conf
Systolic algorithms for tree pattern matching.
ICCD
Abdel Ejnioui, N. Ranganathan
1995 J jnl
VLSI Architectures for High-Speed Range Estimation.
IEEE Trans. Pattern Anal. Mach. Intell.
Raghu Sastry, N. Ranganathan, Ramesh C. Jain
1994 — conf
A Parallel Algorithm and Architecture for Robot Path Planning.
IPPS
N. Ranganathan, Bharadwaj Parthasarathy, Ken Hughes
1994 C conf
A VLSI Chip for Template Matching.
ICCD
N. Ranganathan, Satish Venugopal
1994 — conf
A lossless image compression algorithm using variable block size segmentation.
ICPR (3)
N. Ranganathan, Steve G. Romaniuk, Kameswara Rao Namuduri
1994 Misc conf
ACE: A VLSI Chip for Galois Field GF (2
VLSI Design
Mario Kovac, N. Ranganathan
1994 — conf
An Efficient VLSI Architecture for Template Matching.
ICPP (1)
N. Ranganathan, Satish Venugopal
1994 — conf
An efficient VLSI architecture for template matching based on moment preserving pattern matching.
ICPR (3)
N. Ranganathan, Satish Venugopal
1994 J jnl
Modeling Sensor Confidence for Sensor Integration Tasks.
Int. J. Pattern Recognit. Artif. Intell.
Ken Hughes, N. Ranganathan
1994 J jnl
VLSI Architectures for Pattern Matching.
Int. J. Pattern Recognit. Artif. Intell.
N. Ranganathan, Raghu Sastry
1993 — conf
A Model for Determining Sensor Confidence.
ICRA (2)
Ken Hughes, N. Ranganathan
1993 C conf
A Systolic Array for Approximate String Matching.
ICCD
Raghu Sastry, N. Ranganathan
1993 Misc conf
Hardware Algorithms for Polygon Matching.
VLSI Design
Raghu Sastry, N. Ranganathan, Horst Bunke
1993 J jnl
MARVLE: a VLSI chip for data compression using tree-based codes.
IEEE Trans. Very Large Scale Integr. Syst.
Amar Mukherjee, N. Ranganathan, Jeffrey W. Flieder, Tinku Acharya
1993 Misc conf
SIGMA: A VLSI Chip for Galois Field GF(2
VLSI Design
Mario Kovac, N. Ranganathan, M. Varanasi
1993 J jnl
SIGMA: a VLSI systolic array implementation of a Galois field GF(2
IEEE Trans. Very Large Scale Integr. Syst.
Mario Kovac, N. Ranganathan, M. Varanasi
1993 C conf
SMAC: A Scene Matching Chip.
ICCD
N. Ranganathan, Raghu Sastry, Raguveer Venkatesan, Joseph W. Yoder, David C. Keezer
1993 — conf
VLSI Architectures for Depth Estimation Using Intensity Gradient Analysis.
IPPS
Raghu Sastry, N. Ranganathan, Ramesh C. Jain
1993 J jnl
VLSI architectures for polygon recognition.
IEEE Trans. Very Large Scale Integr. Syst.
Raghu Sastry, N. Ranganathan, Horst Bunke
1992 Misc conf
A CMOS VLSI Chip for Motion Detection.
VLSI Design
N. Ranganathan, Rajiv Mehrotra, S. Kurji
1992 — conf
A Systolic Algorithm and Architecture for Galois Field Arithmetic.
IPPS
Mario Kovac, N. Ranganathan, M. Varanasi
1992 Misc conf
A Two-dimensional Systolic Array Processor for Image Processing.
VLSI Design
N. Ranganathan, Minesh I. Patel, Patrick McCabe
1992 — conf
A VLSI architecture for hierarchical scene matching.
ICPR (4)
R. Venkatesan, Raghu Sastry, N. Ranganathan
1992 — conf
A VLSI hardware accelerator for dynamic time warping.
ICPR (4)
V. K. Sundaresan, Sanjay Nichani, N. Ranganathan, Ravi Sankar
1992 J jnl
A VLSI systolic array processor chip for computing joins in a relational database.
Microprocess. Microsystems
N. Ranganathan, K. R. Balaji, Hassan N. Srinidhi
1992 — conf
Edge detection models based on Gabor filters.
ICPR (3)
Kameswara Rao Namuduri, Rajiv Mehrotra, N. Ranganathan
1992 C conf
MARVLE: A VLSI Chip for Variable Length Encoding and Decoding.
ICCD
Amar Mukherjee, Jeffrey W. Flieder, N. Ranganathan
1992 — conf
SIBA: a VLSI systolic array chip for image processing.
ICPR (4)
Minesh I. Patel, Patrick McCabe, N. Ranganathan
1992 A conf
trulla : An Algorithm For Path Planning Among Weighted Regions By Localized Propagations.
IROS
Ken Hughes, Alade Tokuta, N. Ranganathan
1991 J jnl
A VLSI architecture for a half-edge-based corner detector.
Mach. Vis. Appl.
N. Ranganathan, Sanjay Nichani, Rajiv Mehrotra
1991 J jnl
A VLSI architecture for dynamic scene analysis.
CVGIP Image Underst.
N. Ranganathan, Rajiv Mehrotra
1991 Misc conf
An architecture to implement multiresolution.
ICASSP
N. Ranganathan, Rajiv Mehrotra, Kameswara Rao Namuduri
1990 — conf
A VLSI architecture for difference picture-based dynamic scene analysis.
ICPR (2)
N. Ranganathan, Rajiv Mehrotra
1990 — conf
A parallel architecture for data compression.
SPDP
Selwyn Henriques, N. Ranganathan
1990 — conf
Effect of Data Compression Hardware on the Performance of a Relational Database Machine.
PARBASE
N. Ranganathan, Hassan N. Srinidhi
1990 — conf
Fast spatiotemporal filters.
ICPR (2)
K. R. Namaduri, Rajiv Mehrotra, N. Ranganathan
1990 C conf
SAP: design of a systolic array processor for computation in vision.
ICCD
Sanjay Nichani, N. Ranganathan
1989 — conf
A VLSI system for difference picture-based motion analysis.
TAI
N. Ranganathan, Rajiv Mehrotra
1989 C conf
Adaptive and pipelined VLSI designs for tree-based codes.
ICCD
Amar Mukherjee, N. Ranganathan, Mostafa A. Bassiouni
1989 J jnl
Enhancing arithmetic and tree-based coding.
Inf. Process. Manag.
Mostafa A. Bassiouni, Amar Mukherjee, N. Ranganathan
1989 A* conf
On Software and Hardware Techniques of Data Engineering.
ICDE
Mostafa A. Bassiouni, Amar Mukherjee, N. Ranganathan
1988 J jnl
A VLSI architecture for computing scale space.
Comput. Vis. Graph. Image Process.
N. Ranganathan, Mubarak Shah
1988 A conf
A scheme for data compression in supercomputers.
SC
Mostafa A. Bassiouni, N. Ranganathan, Amar Mukherjee
1988 B conf
Software and Hardware Enhancement of Arithmetic Coding.
SSDBM
Mostafa A. Bassiouni, N. Ranganathan, Amar Mukherjee