N. Pete Sedcole

29 papers A 4B 7C 1Misc 1Journal 5Unranked 11
YearRankTypeTitle / Venue / Authors
2010 A conf
Degradation in FPGAs: measurement and modelling.
FPGA
Edward A. Stott, Justin S. J. Wong, N. Pete Sedcole, Peter Y. K. Cheung
2010 J jnl
Fault tolerance and reliability in field-programmable gate arrays.
IET Comput. Digit. Tech.
Edward A. Stott, N. Pete Sedcole, Peter Y. K. Cheung
2010 J jnl
Wave-pipelined intra-chip signaling for on-FPGA communications.
Integr.
Terrence S. T. Mak, N. Pete Sedcole, Peter Y. K. Cheung, Wayne Luk
2009 B conf
Compensating for variability in FPGAs by re-mapping and re-placement.
FPL
N. Pete Sedcole, Edward A. Stott, Peter Y. K. Cheung
2009 J jnl
Self-Measurement of Combinatorial Circuit Delays in FPGAs.
ACM Trans. Reconfigurable Technol. Syst.
Justin S. J. Wong, N. Pete Sedcole, Peter Y. K. Cheung
2009 C conf
Throughput Maximization for Wave-pipelined Interconnects using Cascaded Buffers and Transistor Sizing.
ISCAS
Li Wang, Terrence S. T. Mak, N. Pete Sedcole, Peter Y. K. Cheung
2008 — conf
A transition probability based delay measurement method for arbitrary circuits on FPGAs.
FPT
Justin S. J. Wong, N. Pete Sedcole, Peter Y. K. Cheung
2008 — conf
Characterisation of FPGA Clock Variability.
ISVLSI
N. Pete Sedcole, Justin S. J. Wong, Peter Y. K. Cheung
2008 B conf
Combating process variation on FPGAS with a precise at-speed delay measurement method.
FPL
Justin S. J. Wong, Peter Y. K. Cheung, N. Pete Sedcole
2008 B conf
Fault tolerant methods for reliability in FPGAs.
FPL
Edward A. Stott, N. Pete Sedcole, Peter Y. K. Cheung
2008 — conf
Global interconnections in FPGAs: modeling and performance analysis.
SLIP
Terrence S. T. Mak, Crescenzo D'Alessandro, N. Pete Sedcole, Peter Y. K. Cheung, Alexandre Yakovlev, Wayne Luk
2008 A conf
High-throughput interconnect wave-pipelining for global communication in FPGAs.
FPGA
Terrence S. T. Mak, N. Pete Sedcole, Peter Y. K. Cheung, Wayne Luk
2008 — conf
Implementation of Wave-Pipelined Interconnects in FPGAs.
NOCS
Terrence S. T. Mak, Crescenzo D'Alessandro, N. Pete Sedcole, Peter Y. K. Cheung, Alexandre Yakovlev, Wayne Luk
2008 — conf
Interconnection lengths and delays estimation for communication links in FPGAs.
SLIP
Terrence S. T. Mak, N. Pete Sedcole, Peter Y. K. Cheung, Wayne Luk
2008 A conf
Measuring and modeling FPGA clock variability.
FPGA
N. Pete Sedcole, Justin S. J. Wong, Peter Y. K. Cheung
2008 — conf
Modelling and compensating for clock skew variability in FPGAs.
FPT
N. Pete Sedcole, Justin S. J. Wong, Peter Y. K. Cheung
2008 J jnl
Parametric Yield Modeling and Simulations of FPGA Circuits Considering Within-Die Delay Variations.
ACM Trans. Reconfigurable Technol. Syst.
N. Pete Sedcole, Peter Y. K. Cheung
2008 — conf
Wave-pipelined signaling for on-FPGA communication.
FPT
Terrence S. T. Mak, N. Pete Sedcole, Peter Y. K. Cheung, Wayne Luk
2007 — conf
A Hybrid Analog-Digital Routing Network for NoC Dynamic Routing.
NOCS
Terrence S. T. Mak, N. Pete Sedcole, Peter Y. K. Cheung, Wayne Luk, Kai-Pui Lam
2007 A conf
Parametric yield in FPGAs due to within-die delay variations: a quantitative analysis.
FPGA
N. Pete Sedcole, Peter Y. K. Cheung
2007 J jnl
Run-Time Integration of Reconfigurable Video Processing Systems.
IEEE Trans. Very Large Scale Integr. Syst.
N. Pete Sedcole, Peter Y. K. Cheung, George A. Constantinides, Wayne Luk
2007 — conf
Self-characterization of Combinatorial Circuit Delays in FPGAs.
FPT
Justin S. J. Wong, N. Pete Sedcole, Peter Y. K. Cheung
2006 — conf
On-Chip Communication in Run-Time Assembled Reconfigurable Systems.
ICSAMOS
N. Pete Sedcole, Peter Y. K. Cheung, George A. Constantinides, Wayne Luk
2006 B conf
On-FPGA Communication Architectures and Design Factors.
FPL
Terrence S. T. Mak, N. Pete Sedcole, Peter Y. K. Cheung, Wayne Luk
2006 — conf
Within-die delay variability in 90nm FPGAs and beyond.
FPT
N. Pete Sedcole, Peter Y. K. Cheung
2005 B conf
Modular Partial Reconfiguration in Virtex FPGAs.
FPL
N. Pete Sedcole, Brandon Blodget, Tobias Becker, James Anderson, Patrick Lysaght
2004 B conf
A Structured Methodology for System-on-an-FPGA Design.
FPL
N. Pete Sedcole, Peter Y. K. Cheung, George A. Constantinides, Wayne Luk
2004 Misc conf
A Structured System Methodology for FPGA Based System-on-A-Chip Design.
FCCM
N. Pete Sedcole, Peter Y. K. Cheung, George A. Constantinides, Wayne Luk
2003 B conf
A Reconfigurable Platform for Real-Time Embedded Video Image Processing.
FPL
N. Pete Sedcole, Peter Y. K. Cheung, George A. Constantinides, Wayne Luk