N. P. van der Meijs

19 papers A* 5A 7C 1Journal 2Unranked 4
YearRankTypeTitle / Venue / Authors
2011 J jnl
A 26 μ W 8 bit 10 MS/s Asynchronous SAR ADC for Low Energy Radios.
IEEE J. Solid State Circuits
Pieter Harpe, Cui Zhou, Yu Bi, N. P. van der Meijs, Xiaoyan Wang, Kathleen Philips, Guido Dolmans, Harmke de Groot
2011 — conf
Efficient sensitivity-based capacitance modeling for systematic and random geometric variations.
ASP-DAC
Yu Bi, Pieter Harpe, N. P. van der Meijs
2004 A conf
Statistically Aware Buffer Planning.
DATE
Giuseppe S. Garcea, N. P. van der Meijs, Kees-Jan van der Kolk, Ralph H. J. M. Otten
2003 A conf
Simultaneous Analytic Area and Power Optimization for Repeater Insertion.
ICCAD
Giuseppe S. Garcea, N. P. van der Meijs, Ralph H. J. M. Otten
2002 A* conf
Combined BEM/FEM substrate resistance modeling.
DAC
Eelco Schrik, N. P. van der Meijs
2002 A conf
Theoretical and practical validation of combined BEM/FEM substrate resistance modeling.
ICCAD
Eelco Schrik, Patrick M. Dewilde, N. P. van der Meijs
1999 A conf
Virtual screening: a step towards a sparse partial inductance matrix.
ICCAD
A. J. Dammers, N. P. van der Meijs
1997 — conf
Cartesian multipole based numerical integration for 3D capacitance extraction.
ED&TC
U. Geigenmüller, N. P. van der Meijs
1996 A conf
Accurate interconnect modeling: towards multi-million transistor chips as microwave circuits.
ICCAD
N. P. van der Meijs, T. Smedes
1996 A* conf
Extracting Circuit Models for Large RC Interconnections that are Accurate up to a Predefined Signal Frequency.
DAC
P. J. H. Elias, N. P. van der Meijs
1996 — conf
Fast Computation of Substrate Resistances in Large Circuits.
ED&TC
Arjan J. van Genderen, N. P. van der Meijs, T. Smedes
1996 — conf
Including Higher-Order Moments of RC Interconnections in Layout-to-Circuit Extraction.
ED&TC
P. J. H. Elias, N. P. van der Meijs
1996 A* conf
Using Articulation Nodes to Improve the Efficiency of Finite-Element based Resistance Extraction.
DAC
Arjan J. van Genderen, N. P. van der Meijs
1995 C conf
Accurate and efficient layout-to-circuit extraction for high-speed MOS and bipolar/BiCMOS integrated circuits.
ICCD
Frederik Beeftink, Arjan J. van Genderen, N. P. van der Meijs
1995 A* conf
Delayed Frontal Solution for Finite-Element Based Resistance Extraction.
DAC
N. P. van der Meijs, Arjan J. van Genderen
1995 A conf
Extraction of circuit models for substrate cross-talk.
ICCAD
T. Smedes, N. P. van der Meijs, Arjan J. van Genderen
1993 A conf
Hierarchical extraction of 3D interconnect capacitances in large regular VLSI structures.
ICCAD
Arjan J. van Genderen, N. P. van der Meijs
1989 A* conf
An Efficient Finite Element Method for Submicron IC Capacitance Extraction.
DAC
N. P. van der Meijs, Arjan J. van Genderen
1984 J jnl
VLSI circuit reconstruction from mask topology.
Integr.
N. P. van der Meijs, J. T. Fokkema