N. Nalla Anandakumar

21 papers B 1C 1Misc 2Journal 11Unranked 6
YearRankTypeTitle / Venue / Authors
2023 B conf
PSC-Watermark: Power Side Channel Based IP Watermarking Using Clock Gates.
ETS
Upoma Das, M. Sazadur Rahman, N. Nalla Anandakumar, Kimia Zamiri Azar, Fahim Rahman, Mark Tehranipoor, Farimah Farahmandi
2022 J jnl
Design and Analysis of FPGA-based PUFs with Enhanced Performance for Hardware-oriented Security.
ACM J. Emerg. Technol. Comput. Syst.
N. Nalla Anandakumar, Mohammad S. Hashmi, Somitra Kumar Sanadhya
2022 J jnl
Field Programmable Gate Array based elliptic curve Menezes-Qu-Vanstone key agreement protocol realization using Physical Unclonable Function and true random number generator primitives.
IET Circuits Devices Syst.
N. Nalla Anandakumar, Mohammad S. Hashmi, Somitra Kumar Sanadhya
2022 J jnl
Implementation of Efficient XOR Arbiter PUF on FPGA With Enhanced Uniqueness and Security.
IEEE Access
N. Nalla Anandakumar, Mohammad S. Hashmi, Muhammad Akmal Chaudhary
2022 J jnl
PQC-SEP: Power Side-channel Evaluation Platform for Post-Quantum Cryptography Algorithms.
IACR Cryptol. ePrint Arch.
Jungmin Park, N. Nalla Anandakumar, Dipayan Saha, Dhwani Mehta, Nitin Pundir, Fahim Rahman, Farimah Farahmandi, Mark Tehranipoor
2022 J jnl
Rethinking Watermark: Providing Proof of IP Ownership in Modern SoCs.
IACR Cryptol. ePrint Arch.
N. Nalla Anandakumar, M. Sazadur Rahman, Mridha Md Mashahedur Rahman, Rasheed Kibria, Upoma Das, Farimah Farahmandi, Fahim Rahman, Mark Tehranipoor
2021 — conf
FPGA Implementations of Espresso Stream Cipher.
ICECS
Gani Kumisbek, N. Nalla Anandakumar, Mohammad S. Hashmi
2021 J jnl
FPGA-based Physical Unclonable Functions: A comprehensive overview of theory and architectures.
Integr.
N. Nalla Anandakumar, Mohammad S. Hashmi, Mark Tehranipoor
2020 — conf
A Survey of Security Attacks on Silicon Based Weak PUF Architectures.
SSCC
Chintala Yehoshuva, R. Raja Adhithan, N. Nalla Anandakumar
2020 C conf
Design, Implementation and Analysis of Efficient Hardware-Based Security Primitives.
VLSI-SOC
N. Nalla Anandakumar, Somitra Kumar Sanadhya, Mohammad S. Hashmi
2020 J jnl
Efficient and Lightweight FPGA-based Hybrid PUFs with Improved Performance.
Microprocess. Microsystems
N. Nalla Anandakumar, Mohammad S. Hashmi, Somitra Kumar Sanadhya
2020 J jnl
FPGA-Based True Random Number Generation Using Programmable Delays in Oscillator-Rings.
IEEE Trans. Circuits Syst. II Express Briefs
N. Nalla Anandakumar, Somitra Kumar Sanadhya, Mohammad S. Hashmi
2020 — conf
Modeling Attacks and Efficient Countermeasures on Interpose PUF.
FPS
R. Raja Adhithan, N. Nalla Anandakumar
2018 — conf
Key Retrieval from AES Architecture Through Hardware Trojan Horse.
SSCC
Sivappriya Manivannan, N. Nalla Anandakumar, M. Nirmala Devi
2018 J jnl
Reconfigurable Hardware Architecture for Authenticated Key Agreement Protocol Over Binary Edwards Curve.
ACM Trans. Reconfigurable Technol. Syst.
N. Nalla Anandakumar, M. Prem Laxman Das, Somitra Kumar Sanadhya, Mohammad S. Hashmi
2017 Misc conf
Compact Implementations of FPGA-based PUFs with Enhanced Performance.
VLSID
N. Nalla Anandakumar, Mohammad S. Hashmi, Somitra Kumar Sanadhya
2015 J jnl
SCA Resistance Analysis of MAC-PHOTON.
IACR Cryptol. ePrint Arch.
N. Nalla Anandakumar
2015 — conf
SCA Resistance Analysis on FPGA Implementations of Sponge Based \mathttMAC-\mathttPHOTON.
SECITC
N. Nalla Anandakumar
2014 Misc conf
A Very Compact FPGA Implementation of LED and PHOTON.
INDOCRYPT
N. Nalla Anandakumar, Thomas Peyrin, Axel Poschmann
2014 J jnl
A Very Compact FPGA Implementation of LED and PHOTON.
IACR Cryptol. ePrint Arch.
N. Nalla Anandakumar, Thomas Peyrin, Axel Poschmann
2012 — conf
Correlation power analysis attack of AES on FPGA using customized communication protocol.
CCSEIT
N. Nalla Anandakumar, S. Dillibabu