N. Moorthy Muthukrishnan

13 papers C 1Misc 1Unranked 11
YearRankTypeTitle / Venue / Authors
2018 — conf
Comparison of Voltage Charging Techniques to Increase the Life of Lead Acid Batteries.
iSES
Madhuri Bayya, U. M. Rao, BVVSN Prabhakar Rao, N. Moorthy Muthukrishnan
2012 — conf
A Modified Twin Precision Multiplier with 2D Bypassing Technique.
ISED
Syed Ershad Ahmed, Sibi Abraham, Sreehari Veeramachaneni, N. Moorthy Muthukrishnan, M. B. Srinivas
2012 — conf
Design and Analysis of Reversible Ripple, Prefix and Prefix-Ripple Hybrid Adders.
ISVLSI
Chetan Kumar Vudadha, P. Sai Phaneendra, Syed Ershad Ahmed, Sreehari Veeramachaneni, N. Moorthy Muthukrishnan, Mandalika B. Srinivas
2012 — conf
Design of Prefix-Based Optimal Reversible Comparator.
ISVLSI
Chetan Kumar Vudadha, P. Sai Phaneendra, Sreehari Veeramachaneni, Syed Ershad Ahmed, N. Moorthy Muthukrishnan, Mandalika B. Srinivas
2012 Misc conf
Low-Power Self Reconfigurable Multiplexer Based Decoder for Adaptive Resolution Flash ADCs.
VLSI Design
Chetan Kumar Vudadha, Goutham Makkena, M. Venkata Swamy Nayudu, P. Sai Phaneendra, Syed Ershad Ahmed, Sreehari Veeramachaneni, N. Moorthy Muthukrishnan, M. B. Srinivas
2011 — conf
A Multiple-Bandwidth 10-bit SAR Analog to Digital Converter.
ISED
Mahesh Kumar Adimulam, Krishna Kumar Movva, Sreehari Veeramachaneni, N. Moorthy Muthukrishnan, M. B. Srinivas
2011 — conf
A Prefix Based Reconfigurable Adder.
ISVLSI
Chetan Kumar V., Sai Phaneendra P., Syed Ershad Ahmed, Sreehari Veeramachaneni, N. Moorthy Muthukrishnan, M. B. Srinivas
2011 — conf
A Reconfigurable INC/DEC/2's Complement/Priority Encoder Circuit with Improved Decision Block.
ISED
Chetan Kumar V., P. Sai Phaneendra, Syed Ershad Ahmed, Sreehari Veeramachaneni, N. Moorthy Muthukrishnan, M. B. Srinivas
2011 C conf
A Unified Architecture for BCD and Binary Adder/Subtractor.
DSD
Chetan Kumar V., P. Sai Phaneendra, Syed Ershad Ahmed, Sreehari Veeramachaneni, N. Moorthy Muthukrishnan, M. B. Srinivas
2011 — conf
Increment/decrement/2's complement/priority encoder circuit for varying operand lengths.
ISCIT
P. Sai Phaneendra, Chetan Kumar Vudadha, Syed Ershad Ahmed, Sreehari Veeramachaneni, N. Moorthy Muthukrishnan, M. B. Srinivas
2010 — conf
A Novel, Variable Resolution Flash ADC with Sub Flash Architecture.
ISVLSI
Mahesh Kumar Adimulam, Sreehari Veeramachaneni, N. Moorthy Muthukrishnan, M. B. Srinivas
2010 — conf
A low power, variable resolution two-step flash ADC.
ACM Great Lakes Symposium on VLSI
Mahesh Kumar Adimulam, Krishna Kumar Movva, Sreehari Veeramachaneni, N. Moorthy Muthukrishnan, M. B. Srinivas
2010 — conf
Low power, variable resolution pipelined analog to Digital converter with sub flash architecture.
APCCAS
Mahesh Kumar Adimulam, Krishna Kumar Movva, Sreehari Veeramachaneni, N. Moorthy Muthukrishnan, Mandalika B. Srinivas