Mário P. Véstias

66 papers B 15C 10Journal 21Unranked 18

Year	Rank	Type	Title / Venue / Authors
2024	—	`ed.`	Applied Reconfigurable Computing. Architectures, Tools, and Applications - 20th International Symposium, ARC 2024, Aveiro, Portugal, March 20-22, 2024, Proceedings ARC Iouliia Skliarova, Piedad Brox Jiménez, Mário P. Véstias, Pedro C. Diniz
2024	J	`jnl`	Designing Deep Learning Models on FPGA with Multiple Heterogeneous Engines. ACM Trans. Reconfigurable Technol. Syst. Miguel Reis, Mário P. Véstias, Horácio C. Neto
2024	J	`jnl`	Enhancing Urban Intersection Efficiency: Visible Light Communication and Learning-Based Control for Traffic Signal Optimization and Vehicle Management. Symmetry Manuel Augusto M. Vieira, Gonçalo Galvão, Manuela Vieira, Paula Louro, Mário P. Véstias, Pedro Vieira
2024	—	`conf`	LiDAR 3D Object Detection in FPGA with Low Bitwidth Quantization. ARC Henrique B. Brum, Mário P. Véstias, Horácio C. Neto
2024	C	`conf`	PT-Float: A Floating-Point Unit with Dynamically Varying Exponent and Fraction Sizes. ARITH José T. de Sousa, João D. Lopes, Micaela Serôdio, Horácio C. Neto, Mário P. Véstias
2023	J	`jnl`	Efficient Design of Low Bitwidth Convolutional Neural Networks on FPGA with Optimized Dot Product Units. ACM Trans. Reconfigurable Technol. Syst. Mário P. Véstias, Rui Policarpo Duarte, José T. de Sousa, Horácio C. Neto
2023	J	`jnl`	Energy-Efficient and Real-Time Wearable for Wellbeing-Monitoring IoT System Based on SoC-FPGA. Algorithms Maria Inês Frutuoso, Horácio C. Neto, Mário P. Véstias, Rui Policarpo Duarte
2023	J	`jnl`	Smart Embedded System for Skin Cancer Classification. Future Internet Pedro F. Durães, Mário P. Véstias
2022	J	`jnl`	A Review of Synthetic-Aperture Radar Image Formation Algorithms and Implementations: A Computational Perspective. Remote. Sens. Helena Cruz, Mário P. Véstias, José Monteiro, Horácio C. Neto, Rui Policarpo Duarte
2022	J	`jnl`	Onboard Processing of Synthetic Aperture Radar Backprojection Algorithm in FPGA. IEEE J. Sel. Top. Appl. Earth Obs. Remote. Sens. David Mota, Helena Cruz, Pedro R. Miranda, Rui Policarpo Duarte, José T. de Sousa, Horácio C. Neto, Mário P. Véstias
2021	J	`jnl`	A Full Featured Configurable Accelerator for Object Detection With YOLO. IEEE Access Daniel Pestana, Pedro R. Miranda, João D. Lopes, Rui Policarpo Duarte, Mário P. Véstias, Horácio C. Neto, José T. de Sousa
2021	J	`jnl`	Configurable Hardware Core for IoT Object Detection. Future Internet Pedro R. Miranda, Daniel Pestana, João D. Lopes, Rui Policarpo Duarte, Mário P. Véstias, Horácio C. Neto, José T. de Sousa
2021	J	`jnl`	Decimal Multiplication in FPGA with a Novel Decimal Adder/Subtractor. Algorithms Mário P. Véstias, Horácio C. Neto
2021	J	`jnl`	Efficient Design of Pruned Convolutional Neural Networks on FPGA. J. Signal Process. Syst. Mário P. Véstias
2021	J	`jnl`	IOb-Cache: A High-Performance Configurable Open-Source Cache. Algorithms João V. Roque, João D. Lopes, Mário P. Véstias, José T. de Sousa
2020	J	`jnl`	A Configurable Architecture for Running Hybrid Convolutional Neural Networks in Low-Density FPGAs. IEEE Access Mário P. Véstias, Rui Policarpo Duarte, José T. de Sousa, Horácio C. Neto
2020	J	`jnl`	A fast and scalable architecture to run convolutional neural networks in low density FPGAs. Microprocess. Microsystems Mário P. Véstias, Rui Policarpo Duarte, José T. de Sousa, Horácio C. Neto
2020	J	`jnl`	Hyperspectral Compressive Sensing With a System-On-Chip FPGA. IEEE J. Sel. Top. Appl. Earth Obs. Remote. Sens. José M. P. Nascimento, Mário P. Véstias, Gabriel Martín
2020	—	`conf`	Implementing CNNs Using a Linear Array of Full Mesh CGRAs. ARC Valter Mário, João D. Lopes, Mário P. Véstias, José T. de Sousa
2020	J	`jnl`	Moving Deep Learning to the Edge. Algorithms Mário P. Véstias, Rui Policarpo Duarte, José T. de Sousa, Horácio C. Neto
2020	—	`ch.`	Processing Systems for Deep Learning Inference on Edge Devices. Convergence of Artificial Intelligence and the Internet of Things Mário P. Véstias
2019	J	`jnl`	A Survey of Convolutional Neural Networks on Edge with Reconfigurable Computing. Algorithms Mário P. Véstias
2019	—	`conf`	Exploring Data Size to Run Convolutional Neural Networks in Low Density FPGAs. ARC Ana Gonçalves, Tiago Peres, Mário P. Véstias
2019	—	`conf`	Faster Convolutional Neural Networks in Low Density FPGAs Using Block Pruning. ARC Tiago Peres, Ana Gonçalves, Mário P. Véstias
2019	B	`conf`	Hybrid Dot-Product Calculation for Convolutional Neural Networks in FPGA. FPL Mário P. Véstias, Rui Policarpo Duarte, José T. de Sousa, Horácio C. Neto
2019	C	`conf`	Low Energy Heterogeneous Computing with Multiple RISC-V and CGRA Cores. ISCAS Luís Fiolhais, Fernando M. Gonçalves, Rui Policarpo Duarte, Mário P. Véstias, José T. de Sousa
2018	J	`jnl`	Improving the area of fast parallel decimal multipliers. Microprocess. Microsystems Mário P. Véstias, Horácio C. Neto
2018	B	`conf`	Lite-CNN: A High-Performance Architecture to Execute CNNs in Low Density FPGAs. FPL Mário P. Véstias, Rui Policarpo Duarte, José T. de Sousa, Horácio C. Neto
2017	J	`jnl`	Decimal addition on FPGA based on a mixed BCD/excess-6 representation. Microprocess. Microsystems Horácio C. Neto, Mário P. Véstias
2017	B	`conf`	K-means clustering on CGRA. FPL João D. Lopes, José T. de Sousa, Horácio C. Neto, Mário P. Véstias
2017	B	`conf`	Parallel dot-products for deep learning on FPGA. FPL Mário P. Véstias, Rui Policarpo Duarte, José T. de Sousa, Horácio C. Neto
2016	B	`conf`	Multi-core for K-means clustering on FPGA. FPL Jose Canilho, Mário P. Véstias, Horácio C. Neto
2016	—	`conf`	XtokaxtikoX: A stochastic computing-based autonomous cyber-physical system. ICRC Rui Policarpo Duarte, Horácio C. Neto, Mário P. Véstias
2015	J	`jnl`	Designing Hardware/Software Systems for Embedded High-Performance Computing. CoRR Mário P. Véstias, Rui Policarpo Duarte, Horácio C. Neto
2015	B	`conf`	Enhancing stochastic computations via process variation. FPL Rui Policarpo Duarte, Mário P. Véstias, Horácio C. Neto
2015	C	`conf`	FPGA-based architecture for hyperspectral unmixing. IGARSS José M. P. Nascimento, Mário P. Véstias, Gabriel Martín
2015	C	`conf`	Sparse Matrix Multiplication on a Reconfigurable Many-Core Architecture. DSD João Pinhão, Wilson José, Horácio C. Neto, Mário P. Véstias
2015	C	`conf`	Using Dynamic Reconfiguration to Reduce the Area of a JPEG Decoder on FPGA. DSD Tiago Rodrigues, Mário P. Véstias
2014	J	`jnl`	A Many-Core Overlay for High-Performance Embedded Computing on FPGAs. CoRR Mário P. Véstias, Horácio C. Neto
2014	B	`conf`	Efficient implementation of a single-precision floating-point arithmetic unit on FPGA. FPL Wilson José, Ana Rita Silva, Horácio C. Neto, Mário P. Véstias
2014	B	`conf`	Trends of CPU, GPU and FPGA for high-performance computing. FPL Mário P. Véstias, Horácio C. Neto
2013	B	`conf`	A reconfigurable computing architecture using magnetic tunneling junction memories. FPL Victor Silva, Jorge R. Fernandes, Mário P. Véstias, Horácio C. Neto
2013	B	`conf`	Analysis of matrix multiplication on high density Virtex-7 FPGA. FPL Wilson José, Ana Rita Silva, Horácio C. Neto, Mário P. Véstias
2013	—	`conf`	Design of a massively parallel computing architecture for dense matrix multiplication. LASCAS Wilson José, Ana Rita Silva, Mário P. Véstias, Horácio C. Neto
2013	—	`conf`	Design of a multiband full-rate ultra-wideband receiver in FPGA. LASCAS Mário P. Véstias, Horácio C. Neto, Helena Sarmento
2013	—	`conf`	Very low resource table-based FPGA evaluation of elementary functions. ReConFig Horácio C. Neto, Mário P. Véstias
2012	—	`conf`	A High-Performance Reconfigurable Computing architecture using a magnetic configuration memory. ReConFig Victor Silva, Jorge R. Fernandes, Mário P. Véstias, Horácio C. Neto
2012	—	`conf`	Design and test of a MIMO Receiver based on the Alamouti scheme in FPGA. ICCE-Berlin Mário P. Véstias
2012	C	`conf`	Design of High-Speed Viterbi Decoders on Virtex-6 FPGAs. DSD Mário P. Véstias, Horácio C. Neto, Helena Sarmento
2012	—	`conf`	Design of an IEEE 802.15.3c baseband processor in FPGA. ICCE-Berlin Mário P. Véstias, Helena Sarmento
2012	—	`conf`	Non-volatile memory circuits for FIMS and TAS writing techniques on magnetic tunnelling junctions. ICECS Victor Silva, Mário P. Véstias, Horácio C. Neto, Jorge R. Fernandes
2012	C	`conf`	Parallel Decimal Multipliers and Squarers Using Karatsuba-Ofman's Algorithm. DSD Mário P. Véstias, Horácio C. Neto
2012	B	`conf`	Sliding block Viterbi decoders in FPGA. FPL Mário P. Véstias, Horácio C. Neto, Helena Sarmento
2012	—	`conf`	Tradeoffs in the design of sliding block Viterbi decoders for MB-OFDM UWB systems. ICCE-Berlin Mário P. Véstias, Helena Sarmento
2011	B	`conf`	Revisiting the Newton-Raphson Iterative Method for Decimal Division. FPL Mário P. Véstias, Horácio C. Neto
2009	C	`conf`	Double-precision Gauss-Jordan Algorithm with Partial Pivoting on FPGAs. DSD Rui Policarpo Duarte, Horácio C. Neto, Mário P. Véstias
2009	C	`conf`	Run-Time Reconfigurable Array Using Magnetic RAM. DSD Victor Silva, Luís Bica Oliveira, Jorge R. Fernandes, Mário P. Véstias, Horácio C. Neto
2008	B	`conf`	Decimal multiplier on FPGA using embedded binary multipliers. FPL Horácio C. Neto, Mário P. Véstias
2008	—	`conf`	Multiplier-based double precision floating point divider according to the IEEE-754 standard. ARC Vítor Silva, Rui Policarpo Duarte, Mário P. Véstias, Horácio C. Neto
2007	B	`conf`	Router Design for Application Specific Networks-on-Chip on Reconfigurable Systems. FPL Mário P. Véstias, Horácio C. Neto
2006	B	`conf`	A Generic Network-on-Chip Architecture for Reconfigurable Systems: Implementation and Evaluation. FPL Mário P. Véstias, Horácio C. Neto
2006	—	`conf`	Area and performance optimization of a generic network-on-chip architecture. SBCCI Mário P. Véstias, Horácio C. Neto
2006	—	`conf`	Area/Performance Improvement of NoC Architectures. ARC Mário P. Véstias, Horácio C. Neto
2006	—	`conf`	Co-synthesis of a configurable SoC platform based on a network on chip architecture. ASP-DAC Mário P. Véstias, Horácio C. Neto
2003	—	`conf`	DALI: A Methodology for the Co-Design of Dataflow Applications on Hardware/Software Architectures. SBCCI Mário P. Véstias, Horácio C. Neto
2002	C	`conf`	System-Level Co-Synthesis of Dataflow Dominated Applications on Reconfigurable Hardware/Software Architectures. IEEE International Workshop on Rapid System Prototyping Mário P. Véstias, Horácio C. Neto