Máire McLoone

23 papers A 1B 3C 2Misc 1Journal 6Unranked 9

Year	Rank	Type	Title / Venue / Authors
2017	J	`jnl`	Evaluation of Large Integer Multiplication Methods on Hardware. IEEE Trans. Computers Ciara Rafferty, Máire McLoone, Neil Hanley
2007	J	`jnl`	High-speed & Low Area Hardware Architectures of the Whirlpool Hash Function. J. VLSI Signal Process. Máire McLoone, Ciaran McIvor
2007	C	`conf`	Identity Based Public Key Exchange (IDPKE) for Wireless Ad Hoc Networks. SECRYPT Clare McGrath, Ghazanfar Ali Safdar, Máire McLoone
2007	J	`jnl`	MONET Special Issue on Next Generation Hardware Architectures for Secure Mobile Computing. Mob. Networks Appl. Nicolas Sklavos, Máire McLoone, Xinmiao Zhang
2007	C	`conf`	New Architectures for Low-Cost Public Key Cryptography on RFID Tags. ISCAS Máire McLoone, Matthew J. B. Robshaw
2007	B	`conf`	Public Key Cryptography and RFID Tags. CT-RSA Máire McLoone, Matthew J. B. Robshaw
2006	—	`conf`	An Adaptable And Scalable Asymmetric Cryptographic Processor. ASAP Neil Smyth, Máire McLoone, John V. McCanny
2006	J	`jnl`	Hardware Elliptic Curve Cryptographic Processor Over $\rm GF(p)$. IEEE Trans. Circuits Syst. I Regul. Pap. Ciaran McIvor, Máire McLoone, John V. McCanny
2006	—	`conf`	Limitations of existing wireless networks authentication and key management techniques for MANETs. ISCN Ghazanfar Ali Safdar, Clare McGrath, Máire McLoone
2006	J	`jnl`	WLAN security processor. IEEE Trans. Circuits Syst. I Regul. Pap. Neil Smyth, Máire McLoone, John V. McCanny
2005	—	`conf`	High-Radix Systolic Modular Multiplication on Reconfigurable Hardware. FPT Ciaran McIvor, Máire McLoone, John V. McCanny
2005	—	`conf`	High-Speed Hardware Architectures of the Whirlpool Hash Function. FPT Máire McLoone, Ciaran McIvor, Aidan Savage
2005	—	`conf`	Reconfigurable Instruction Interface Architecture for Private-Key Cryptography on the Altera Nios-II Processor. AICT/SAPIR/ELETE P. Moore, Máire McLoone, Sakir Sezer
2004	—	`conf`	Coarsely integrated operand scanning (CIOS) architecture for high-speed Montgomery modular multiplication. FPT Máire McLoone, Ciaran McIvor, John V. McCanny
2004	Misc	`conf`	FPGA Montgomery Multiplier Architectures - A Comparison. FCCM Ciaran McIvor, Máire McLoone, John V. McCanny
2004	—	`conf`	FPGA Montgomery modular multiplication architectures suitable for ECCs over GF(p). ISCAS (3) Ciaran McIvor, Máire McLoone, John V. McCanny
2003	—	`conf`	A high-speed, low latency RSA decryption silicon core. ISCAS (4) Ciaran McIvor, Máire McLoone, John V. McCanny
2003	J	`jnl`	Rijndael FPGA Implementations Utilising Look-Up Tables. J. VLSI Signal Process. Máire McLoone, John V. McCanny
2003	B	`conf`	Very High Speed 17 Gbps SHACAL Encryption Architecture. FPL Máire McLoone, John V. McCanny
2002	—	`conf`	Efficient single-chip implementation of SHA-384 and SHA-512. FPT Máire McLoone, John V. McCanny
2002	—	`—`	Generic silicon architectures for encryption algorithm. Máire McLoone
2001	A	`conf`	High Performance Single-Chip FPGA Rijndael Algorithm Implementations. CHES Máire McLoone, John V. McCanny
2001	B	`conf`	Single-Chip FPGA Implementation of the Advanced Encryption Standard Algorithm. FPL Máire McLoone, John V. McCanny