Mythri Alle

18 papers A* 1B 1C 1Misc 2Journal 2Unranked 11
YearRankTypeTitle / Venue / Authors
2013 C conf
GeCoS: A framework for prototyping custom hardware design flows.
SCAM
Antoine Floch, Tomofumi Yuki, Ali El Moussawi, Antoine Morvan, Kevin J. M. Martin, Maxime Naullet, Mythri Alle, Ludovic L'Hours, Nicolas Simon, Steven Derrien, François Charot, Christophe Wolinski, Olivier Sentieys
2013 A* conf
Runtime dependency analysis for loop pipelining in high-level synthesis.
DAC
Mythri Alle, Antoine Morvan, Steven Derrien
2011 J jnl
Data Flow Graph Partitioning Algorithms and Their Evaluations for Optimal Spatio-temporal Computation on a Coarse Grain Reconfigurable Architecture.
IPSJ Trans. Syst. LSI Des. Methodol.
Ratna Krishnamoorthy, Saptarsi Das, Keshavan Varadarajan, Mythri Alle, Masahiro Fujita, Soumitra Kumar Nandy, Ranjani Narayan
2011 — conf
Dataflow Graph Partitioning for Optimal Spatio-Temporal Computation on a Coarse Grain Reconfigurable Architecture.
ARC
Ratna Krishnamoorthy, Keshavan Varadarajan, Masahiro Fujita, Mythri Alle, S. K. Nandy, Ranjani Narayan
2010 — conf
Accelerating Numerical Linear Algebra Kernels on a Scalable Run Time Reconfigurable Platform.
ISVLSI
Prasenjit Biswas, Pramod P. Udupa, Rajdeep Mondal, Keshavan Varadarajan, Mythri Alle, S. K. Nandy, Ranjani Narayan
2010 — conf
Design space exploration of systolic realization of QR factorization on a runtime reconfigurable platform.
ICSAMOS
Prasenjit Biswas, Keshavan Varadarajan, Mythri Alle, S. K. Nandy, Ranjani Narayan
2010 — conf
Enhancements for variable N-point streaming FFT/IFFT on REDEFINE, a runtime reconfigurable architecture.
ICSAMOS
N. Thambi Prashank, M. Prasadarao, Avinaba Dutta, Keshavan Varadarajan, Mythri Alle, S. K. Nandy, Ranjani Narayan
2010 Misc conf
Towards minimizing execution delays on dynamically reconfigurable processors: a case study on REDEFINE.
CASES
Ratna Krishnamoorthy, Keshavan Varadarajan, Ganesh Garga, Mythri Alle, S. K. Nandy, Ranjani Narayan, Masahiro Fujita
2009 — conf
An Input Triggered Polymorphic ASIC for H.264 Decoding.
ASAP
Adarsha Rao, Mythri Alle, Sainath V, Reyaz Shaik, Rajashekhar Chowhan, Sreeramula Sankaraiah, Sravanthi Mantha, S. K. Nandy, Ranjani Narayan
2009 — conf
Compiling Techniques for Coarse Grained Runtime Reconfigurable Architectures.
ARC
Mythri Alle, Keshavan Varadarajan, Alexander Fell, S. K. Nandy, Ranjani Narayan
2009 J jnl
REDEFINE: Runtime reconfigurable polymorphic ASIC.
ACM Trans. Embed. Comput. Syst.
Mythri Alle, Keshavan Varadarajan, Alexander Fell, C. Ramesh Reddy, Joseph Nimmy, Saptarsi Das, Prasenjit Biswas, Jugantor Chetia, Adarsha Rao, S. K. Nandy, Ranjani Narayan
2009 Misc conf
Streaming FFT on REDEFINE-v2: an application-architecture design space exploration.
CASES
Alexander Fell, Mythri Alle, Keshavan Varadarajan, Prasenjit Biswas, Saptarsi Das, Jugantor Chetia, S. K. Nandy, Ranjani Narayan
2008 — conf
Architecture of a polymorphic ASIC for interoperability across multi-mode H.264 decoders.
ASAP
Adarsha Rao, Mythri Alle, S. K. Nandy, Ranjani Narayan
2008 — conf
RECONNECT: A NoC for polymorphic ASICs using a low overhead single cycle router.
ASAP
Joseph Nimmy, C. Ramesh Reddy, Keshavan Varadarajan, Mythri Alle, Alexander Fell, S. K. Nandy, Ranjani Narayan
2008 — conf
Realizing a flexible constraint length Viterbi decoder for software radio on a de Bruijn interconnection network.
SoC
Ganesh Garga, Mythri Alle, Keshavan Varadarajan, S. K. Nandy, H. S. Jamadagni
2008 — conf
Synthesis of application accelerators on Runtime Reconfigurable Hardware.
ASAP
Mythri Alle, Keshavan Varadarajan, Ramesh C. Ramesh, Joseph Nimmy, Alexander Fell, Adarsha Rao, S. K. Nandy, Ranjani Narayan
2007 B conf
REDEFINE: Architecture of a SoC Fabric for Runtime Composition of Computation Structures.
FPL
A. N. Satrawala, Keshavan Varadarajan, Mythri Alle, S. K. Nandy, Ranjani Narayan
2006 — conf
High Performance VLSI Architecture Design for H.264 CAVLC Decoder.
ASAP
Mythri Alle, Jayanta Biswas, S. K. Nandy