Myounggon Kang

13 papers Journal 12Unranked 1
YearRankTypeTitle / Venue / Authors
2025 J jnl
Analysis of Bias Temperature Instability in Peripheral CMOS Devices for Low-Temperature Memory Applications.
IEEE Access
Jung Rae Cho, Seungwon Go, Jingyu Park, Tae Jun Yang, Seonhaeng Lee, Namhyun Lee, Dong Keun Lee, Yoon Kim, Myounggon Kang, Rock-Hyun Baek, Changhyun Kim, Sangwan Kim, Dae Hwan Kim
2024 J jnl
Current-Voltage Modeling of DRAM Cell Transistor Using Genetic Algorithm and Deep Learning.
IEEE Access
Jun Hui Park, Jung Nam Kim, Seonhaeng Lee, Gang-Jun Kim, Namhyun Lee, Rock-Hyun Baek, Dae Hwan Kim, Changhyun Kim, Myounggon Kang, Yoon Kim
2023 J jnl
Analysis of Logic-in-Memory Full Adder Circuit With Floating Gate Field Effect Transistor (FGFET).
IEEE Access
Sueyeon Kim, Insoo Choi, Sangki Cho, Myounggon Kang, Seungjae Baik, Changho Ra, Jongwook Jeon
2020 J jnl
A Radiation-Hardened SAR ADC with Delay-Based Dual Feedback Flip-Flops for Sensor Readout Systems.
Sensors
Duckhoon Ro, Changhong Min, Myounggon Kang, Ik Joon Chang, Hyung-Min Lee
2017 J jnl
Characterization of oxide trap density with the charge pumping technique in dual-layer gate oxide.
IEICE Electron. Express
Younghwan Son, Yoon Kim, Myounggon Kang
2017 J jnl
Investigation of capture and emission dependence between individual traps from complex random telegraph signal noise analysis.
IEICE Electron. Express
Younghwan Son, Yoon Kim, Myounggon Kang
2011 J jnl
The novel SCR-based ESD protection with low triggering and high holding voltages.
Microelectron. J.
Myounggon Kang, Ki-Whan Song, Byung-Gook Park, Hyungcheol Shin
2010 J jnl
A Low Power and Area Scalable High Voltage Switch Technique for Low Operation Voltage in MLC NAND Flash Memory.
IEICE Trans. Electron.
Myounggon Kang, Ki-Tae Park, Youngsun Song, Sungsoo Lee, Yunheub Song, Youngho Lim
2010 J jnl
Boosted Bit Line Program Scheme for Low Operating Voltage MLC NAND Flash Memory.
IEICE Trans. Electron.
Youngsun Song, Ki-Tae Park, Myounggon Kang, Yunheub Song, Sungsoo Lee, Youngho Lim, Kang-Deog Suh
2010 J jnl
Dynamic Vpass Controlled Program Scheme and Optimized Erase Vth Control for High Program Inhibition in MLC NAND Flash Memories.
IEEE J. Solid State Circuits
Ki-Tae Park, Youngsun Song, Myounggon Kang, Sungsoo Lee, Youngho Lim, Kang-Deog Suh, Chilhee Chung
2009 J jnl
A Fully Performance Compatible 45 nm 4-Gigabit Three Dimensional Double-Stacked Multi-Level NAND Flash Memory With Shared Bit-Line Structure.
IEEE J. Solid State Circuits
Ki-Tae Park, Myounggon Kang, Soonwook Hwang, Doo-Gon Kim, Hoosung Cho, Youngwook Jeong, Yong-Il Seo, Jae-Hoon Jang, Hansoo Kim, Yeong-Taek Lee, Soon-Moon Jung, Changhyun Kim
2008 — conf
A 45nm 4Gb 3-Dimensional Double-Stacked Multi-Level NAND Flash Memory with Shared Bitline Structure.
ISSCC
Ki-Tae Park, Doo-Gon Kim, Soonwook Hwang, Myounggon Kang, Hoosung Cho, Youngwook Jeong, Yong-Il Seo, Jae-Hoon Jang, Hansoo Kim, Soon-Moon Jung, Yeong-Taek Lee, Changhyun Kim, Won-Seong Lee
2008 J jnl
A Zeroing Cell-to-Cell Interference Page Architecture With Temporary LSB Storing and Parallel MSB Program Scheme for MLC NAND Flash Memories.
IEEE J. Solid State Circuits
Ki-Tae Park, Myounggon Kang, Doogon Kim, Soonwook Hwang, Byung Yong Choi, Yeong-Taek Lee, Changhyun Kim, Kinam Kim