Muya Chang

34 papers A* 1A 2C 2Misc 1Journal 11Unranked 16
YearRankTypeTitle / Venue / Authors
2026 — conf
31.9 Alpha-Vision: A Real-Time Always-on Vision Processor with 787µs Face Detection Latency in <5mW.
ISSCC
Ben Keller, Rangharajan Venkatesan, Steve Dai, Jason Clemons, Matthew Fojtik, Muya Chang, Thierry Tambe, Nathaniel Ross Pinckney, Stephen G. Tell, Qijing Huang, Shalini De Mello, Brucek Khailany
2025 J jnl
An Edge Accelerator With 5 MB of 0.256-pJ/bit Embedded RRAM and a Localization Solver for Bristle Robot Surveillance.
IEEE J. Solid State Circuits
Samuel D. Spetalnick, Ashwin Sanjay Lele, Brian Crafton, Muya Chang, Sigang Ryu, Jong-Hyeok Yoon, Zhijian Hao, Azadeh Ansari, Win-San Khwa, Yu-Der Chih, Meng-Fan Chang, Arijit Raychowdhury
2024 — conf
30.1 A 40nm VLIW Edge Accelerator with 5MB of 0.256pJ/b RRAM and a Localization Solver for Bristle Robot Surveillance.
ISSCC
Samuel D. Spetalnick, Ashwin Sanjay Lele, Brian Crafton, Muya Chang, Sigang Ryu, Jong-Hyeok Yoon, Zhijian Hao, Azadeh Ansari, Win-San Khwa, Yu-Der Chih, Meng-Fan Chang, Arijit Raychowdhury
2024 C conf
A 24/48V to 0.8V-1.2V All-Digital Synchronous Buck Converter with Package-Integrated GaN power FETs and 180nm Silicon Controller IC.
ISCAS
Kaushik Bhattacharyya, Minxiang Gong, Muya Chang, Xin Zhang, Arijit Raychowdhury
2024 — conf
A 28nm Approximate / Binary 6T CAM for Sequence Alignment.
VLSI Technology and Circuits
Brian Crafton, Samuel D. Spetalnick, Muya Chang, Arijit Raychowdhury
2024 J jnl
A Heterogeneous RRAM In-Memory and SRAM Near-Memory SoC for Fused Frame and Event-Based Target Identification and Tracking.
IEEE J. Solid State Circuits
Ashwin Sanjay Lele, Muya Chang, Samuel D. Spetalnick, Brian Crafton, Shota Konno, Zishen Wan, Ashwin Bhat, Win-San Khwa, Yu-Der Chih, Meng-Fan Chang, Arijit Raychowdhury
2024 J jnl
E-Gaze: Gaze Estimation With Event Camera.
IEEE Trans. Pattern Anal. Mach. Intell.
Nealson Li, Muya Chang, Arijit Raychowdhury
2024 J jnl
In-Situ Privacy via Mixed-Signal Perturbation and Hardware-Secure Data Reversibility.
IEEE Trans. Circuits Syst. I Regul. Pap.
Steven Davis, Jianbo Liu, Boyang Cheng, Muya Chang, Ningyuan Cao
2023 — conf
A 2.38 MCells/mm
VLSI Technology and Circuits
Samuel D. Spetalnick, Muya Chang, Shota Konno, Brian Crafton, Ashwin Sanjay Lele, Win-San Khwa, Yu-Der Chih, Meng-Fan Chang, Arijit Raychowdhury
2023 — conf
A 65 nm 1.4-6.7 TOPS/W Adaptive-SNR Sparsity-Aware CIM Core with Load Balancing Support for DL workloads.
CICC
Mustafa Fayez Ali, Indranil Chakraborty, Sakshi Choudhary, Muya Chang, Dong Eun Kim, Arijit Raychowdhury, Kaushik Roy
2023 — conf
A 73.53TOPS/W 14.74TOPS Heterogeneous RRAM In-Memory and SRAM Near-Memory SoC for Hybrid Frame and Event-Based Target Tracking.
ISSCC
Muya Chang, Ashwin Sanjay Lele, Samuel D. Spetalnick, Brian Crafton, Shota Konno, Zishen Wan, Ashwin Bhat, Win-San Khwa, Yu-Der Chih, Meng-Fan Chang, Arijit Raychowdhury
2023 C conf
Live Demonstration: Hybrid RRAM and SRAM SoC for Fused Frame and Event Target Tracking.
ISCAS
Ashwin Sanjay Lele, Muya Chang, Samuel Spetalnick, Yan Fang, Brian Crafton, Shota Konno, Arijit Raychowdhury
2023 A* conf
Neuromorphic Swarm on RRAM Compute-in-Memory Processor for Solving QUBO Problem.
DAC
Ashwin Sanjay Lele, Muya Chang, Samuel D. Spetalnick, Brian Crafton, Arijit Raychowdhury, Yan Fang
2023 A conf
Privacy-by-Sensing with Time-domain Differentially-Private Compressed Sensing.
DATE
Jianbo Liu, Boyang Cheng, Pengyu Zeng, Steven Davis, Muya Chang, Ningyuan Cao
2022 J jnl
A 40-nm 118.44-TOPS/W Voltage-Sensing Compute-in-Memory RRAM Macro With Write Verification and Multi-Bit Encoding.
IEEE J. Solid State Circuits
Jong-Hyeok Yoon, Muya Chang, Win-San Khwa, Yu-Der Chih, Meng-Fan Chang, Arijit Raychowdhury
2022 J jnl
A 40-nm, 64-Kb, 56.67 TOPS/W Voltage-Sensing Computing-In-Memory/Digital RRAM Macro Supporting Iterative Write With Verification and Online Read-Disturb Detection.
IEEE J. Solid State Circuits
Jong-Hyeok Yoon, Muya Chang, Win-San Khwa, Yu-Der Chih, Meng-Fan Chang, Arijit Raychowdhury
2022 — conf
A 40nm 60.64TOPS/W ECC-Capable Compute-in-Memory/Digital 2.25MB/768KB RRAM/SRAM System with Embedded Cortex M3 Microprocessor for Edge Recommendation Systems.
ISSCC
Muya Chang, Samuel D. Spetalnick, Brian Crafton, Win-San Khwa, Yu-Der Chih, Meng-Fan Chang, Arijit Raychowdhury
2022 — conf
A 40nm 64kb 26.56TOPS/W 2.37Mb/mm
ISSCC
Samuel D. Spetalnick, Muya Chang, Brian Crafton, Win-San Khwa, Yu-Der Chih, Meng-Fan Chang, Arijit Raychowdhury
2022 J jnl
A 65 nm Wireless Image SoC Supporting On-Chip DNN Optimization and Real-Time Computation-Communication Trade-Off via Actor-Critical Neuro-Controller.
IEEE J. Solid State Circuits
Ningyuan Cao, Baibhab Chatterjee, Jianbo Liu, Boyang Cheng, Minxiang Gong, Muya Chang, Shreyas Sen, Arijit Raychowdhury
2022 — conf
An Analog Clock-free Compute Fabric base on Continuous-Time Dynamical System for Solving Combinatorial Optimization Problems.
CICC
Muya Chang, Xunzhao Yin, Zoltán Toroczkai, Xiaobo Hu, Arijit Raychowdhury
2022 A conf
Stochastic Mixed-Signal Circuit Design for In-Sensor Privacy.
ICCAD
Ningyuan Cao, Jianbo Liu, Boyang Cheng, Muya Chang
2021 — conf
29.1 A 40nm 64Kb 56.67TOPS/W Read-Disturb-Tolerant Compute-in-Memory/Digital RRAM Macro with Active-Feedback-Based Read and In-Situ Write Verification.
ISSCC
Jong-Hyeok Yoon, Muya Chang, Win-San Khwa, Yu-Der Chih, Meng-Fan Chang, Arijit Raychowdhury
2021 — conf
A 40nm 100Kb 118.44TOPS/W Ternary-weight Computein-Memory RRAM Macro with Voltage-sensing Read and Write Verification for reliable multi-bit RRAM operation.
CICC
Jong-Hyeok Yoon, Muya Chang, Win-San Khwa, Yu-Der Chih, Meng-Fan Chang, Arijit Raychowdhury
2021 J jnl
A 65nm Thermometer-Encoded Time/Charge-Based Compute-in-Memory Neural Network Accelerator at 0.735pJ/MAC and 0.41pJ/Update.
IEEE Trans. Circuits Syst. II Express Briefs
Minxiang Gong, Ningyuan Cao, Muya Chang, Arijit Raychowdhury
2021 J jnl
EM and Power SCA-Resilient AES-256 Through >350× Current-Domain Signature Attenuation and Local Lower Metal Routing.
IEEE J. Solid State Circuits
Debayan Das, Josef Danial, Anupam Golder, Nirmoy Modak, Shovan Maity, Baibhab Chatterjee, Dong-Hyun Seo, Muya Chang, Avinash Varna, Harish K. Krishnamurthy, Sanu Mathew, Santosh Ghosh, Arijit Raychowdhury, Shreyas Sen
2021 — —
Hardware Dynamical System for Solving Optimization Problems.
Muya Chang
2020 — conf
27.3 EM and Power SCA-Resilient AES-256 in 65nm CMOS Through >350× Current-Domain Signature Attenuation.
ISSCC
Debayan Das, Josef Danial, Anupam Golder, Nirmoy Modak, Shovan Maity, Baibhab Chatterjee, Dong-Hyun Seo, Muya Chang, Avinash Varna, Harish Krishnamurthy, Sanu Mathew, Santosh Ghosh, Arijit Raychowdhury, Shreyas Sen
2020 J jnl
A 65-nm 8-to-3-b 1.0-0.36-V 9.1-1.1-TOPS/W Hybrid-Digital-Mixed-Signal Computing Platform for Accelerating Swarm Robotics.
IEEE J. Solid State Circuits
Ningyuan Cao, Muya Chang, Arijit Raychowdhury
2020 — conf
A 65nm Image Processing SoC Supporting Multiple DNN Models and Real-Time Computation-Communication Trade-Off Via Actor-Critical Neuro-Controller.
VLSI Circuits
Ningyuan Cao, Baibhab Chatterjee, Minxiang Gong, Muya Chang, Shreyas Sen, Arijit Raychowdhury
2020 J jnl
OPTIMO: A 65-nm 279-GOPS/W 16-b Programmable Spatial-Array Processor with On-Chip Network for Solving Distributed Optimizations via the Alternating Direction Method of Multipliers.
IEEE J. Solid State Circuits
Muya Chang, Li-Hsiang Lin, Justin Romberg, Arijit Raychowdhury
2019 — conf
A 65nm 1.1-to-9.1TOPS/W Hybrid-Digital-Mixed-Signal Computing Platform for Accelerating Model-Based and Model-Free Swarm Robotics.
ISSCC
Ningyuan Cao, Muya Chang, Arijit Raychowdhury
2019 Misc conf
Efficient Signal Reconstruction via Distributed Least Square Optimization on a Systolic FPGA Architecture.
ICASSP
Muya Chang, Samantak Gangopadhyay, Tomer Hamam, Justin Romberg, Arijit Raychowdhury
2019 — conf
Optimo: A 65Nm 270Mhz 143.2Mw Programmable Spatial-Array-Processor With A Hierarchical Multi-Cast On-Chip Network For Solving Distributed Optimizations.
CICC
Muya Chang, Li-Hsiang Lin, Justin Romberg, Arijit Raychowdhury
2018 — conf
A FeFET Based Processing-In-Memory Architecture for Solving Distributed Least-Square Optimizations.
DRC
Insik Yoon, Muya Chang, Kai Ni, Matthew Jerry, Samantak Gangopadhyay, Gus Henry Smith, Tomer Hamam, Vijayakrishan Narayanan, Justin Romberg, Shih-Lien Lu, Suman Datta, Arijit Raychowdhury