Mutsuo Hidaka

12 papers Journal 10Unranked 2
YearRankTypeTitle / Venue / Authors
2021 J jnl
Fabrication Process for Superconducting Digital Circuits.
IEICE Trans. Electron.
Mutsuo Hidaka, Shuichi Nagasawa
2021 J jnl
Planarized Nb 4-Layer Fabrication Process for Superconducting Integrated Circuits and Its Fabricated Device Evaluation.
IEICE Trans. Electron.
Shuichi Nagasawa, Masamitsu Tanaka, Naoki Takeuchi, Yuki Yamanashi, Shigeyuki Miyajima, Fumihiro China, Taiki Yamae, Koki Yamazaki, Yuta Somei, Naonori Sega, Yoshinao Mizugaki, Hiroaki Myoren, Hirotaka Terai, Mutsuo Hidaka, Nobuyuki Yoshikawa, Akira Fujimaki
2019 J jnl
Foreword.
IEICE Trans. Electron.
Mutsuo Hidaka
2014 J jnl
Design and High-Speed Demonstration of Single-Flux-Quantum Bit-Serial Floating-Point Multipliers Using a 10kA/cm
IEICE Trans. Electron.
Xizhu Peng, Yuki Yamanashi, Nobuyuki Yoshikawa, Akira Fujimaki, Naofumi Takagi, Kazuyoshi Takagi, Mutsuo Hidaka
2014 J jnl
Nb 9-Layer Fabrication Process for Superconducting Large-Scale SFQ Circuits and Its Process Evaluation.
IEICE Trans. Electron.
Shuichi Nagasawa, Kenji Hinode, Tetsuro Satoh, Mutsuo Hidaka, Hiroyuki Akaike, Akira Fujimaki, Nobuyuki Yoshikawa, Kazuyoshi Takagi, Naofumi Takagi
2012 J jnl
Foreword.
IEICE Trans. Electron.
Mutsuo Hidaka
2010 J jnl
100 GHz Demonstrations Based on the Single-Flux-Quantum Cell Library for the 10 kA/cm
IEICE Trans. Electron.
Yuki Yamanashi, Toshiki Kainuma, Nobuyuki Yoshikawa, Irina Kataeva, Hiroyuki Akaike, Akira Fujimaki, Masamitsu Tanaka, Naofumi Takagi, Shuichi Nagasawa, Mutsuo Hidaka
2008 — conf
Applying Low Power Consumption Superconductive Device Technology to Real-Time Waveform Monitoring for Photonic Network.
SAINT
Mutsuo Hidaka, Michitaka Maruyama, Hideo Suzuki
2008 J jnl
Improvements in Fabrication Process for Nb-Based Single Flux Quantum Circuits in Japan.
IEICE Trans. Electron.
Mutsuo Hidaka, Shuichi Nagasawa, Kenji Hinode, Tetsuro Satoh
2008 — conf
Superconductive Single-Flux-Quantum Circuit/System Technology and 40Gb/s Switch System Demonstration.
ISSCC
Yoshihito Hashimoto, Shuichi Nagasawa, Tetsuro Satoh, Kenji Hinode, Hideo Suzuki, Toshiyuki Miyazaki, Mutsuo Hidaka, Nobuyuki Yoshikawa, Hirotaka Terai, Akira Fujimaki
1989 J jnl
570-ps 13-mW Josephson 1-kbit NDRO RAM.
IEEE J. Solid State Circuits
Shuichi Nagasawa, Yoshifusa Wada, Mutsuo Hidaka, Hisanao Tsuge, Iichiro Ishida, Shuichi Tahara
1988 J jnl
AC-and DC-powered subnanosecond 1-kbit Josephson cache memory design.
IEEE J. Solid State Circuits
Yoshifusa Wada, Mutsuo Hidaka, Shuichi Nagasawa, Ichiro Ishida