Mustafa Celik

19 papers A* 3A 4Journal 5Unranked 7
YearRankTypeTitle / Venue / Authors
2025 — conf
A Jamming-Resilient 5G PUCCH Receiver for Small Block Coding Region.
MILCOM
Mustafa Celik, Cagri Goken, Okan Ertürk
2025 J jnl
Physician perspectives on Artificial Intelligence in healthcare: a cross-sectional study of child-focused care in a Turkish tertiary hospital.
Int. J. Medical Informatics
Oguzhan Serin, Banu Fulya Yildirim, Fatma Duman, Kubra Ercorumlu, Rana Yavas, Medine Aysin Tasar, Mustafa Celik
2019 — conf
Cascade Control of SATCOM on the Move (SOTM) Antennas with Jacobian Operator.
ICCMA
Mustafa Celik, Oguz Kaan Hancioglu, Seta Bogosyan, Michal Bastl, Jan Najman, Robert Grepl
2019 — conf
System Identification-Based Dynamics Control for X-Y Pedestal Satellite Antenna.
ICCMA
Baris Aykent, Kadir Koca, Mustafa Celik
2009 A* conf
A parametric approach for handling local variation effects in timing analysis.
DAC
Ayhan A. Mutlu, Jiayong Le, Ruben Molina, Mustafa Celik
2009 — conf
Parametric analysis to determine accurate interconnect extraction corners for design performance.
ISQED
Ayhan A. Mutlu, Jiayong Le, Ruben Molina, Mustafa Celik
2008 J jnl
Defining Statistical Timing Sensitivity for Logic Circuits With Large-Scale Process and Environmental Variations.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst.
Xin Li, Jiayong Le, Mustafa Celik, Lawrence T. Pileggi
2007 — conf
An Exploratory Study on Statistical Timing Analysis and Parametric Yield Optimization.
ISQED
Ayhan A. Mutlu, Kelvin J. Le, Mustafa Celik, Dar-sun Tsien, Garry Shyu, Long-Ching Yeh
2005 A conf
Defining statistical sensitivity for timing optimization of logic circuits with large-scale process and environmental variations.
ICCAD
Xin Li, Jiayong Le, Mustafa Celik, Lawrence T. Pileggi
2001 — conf
A fast analytical technique for estimating the bounds of on-chip clock wire inductance.
CICC
Yi-Chang Lu, Kaustav Banerjee, Mustafa Celik, Robert W. Dutton
2001 A* conf
Min/max On-Chip Inductance Models and Delay Metrics.
DAC
Yi-Chang Lu, Mustafa Celik, Tak Young, Lawrence T. Pileggi
1999 J jnl
Metrics and bounds for phase delay and signal attenuation in RC(L)clock trees.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst.
Mustafa Celik, Lawrence T. Pileggi
1999 A conf
Practical considerations for passive reduction of RLC circuits.
ICCAD
Altan Odabasioglu, Mustafa Celik, Lawrence T. Pileggi
1999 — conf
S2P: A Stable 2-Pole RC Delay and Coupling Noise Metric.
Great Lakes Symposium on VLSI
Emrah Acar, Altan Odabasioglu, Mustafa Celik, Lawrence T. Pileggi
1998 J jnl
PRIMA: passive reduced-order interconnect macromodeling algorithm.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst.
Altan Odabasioglu, Mustafa Celik, Lawrence T. Pileggi
1997 A conf
PRIMA: passive reduced-order interconnect macromodeling algorithm.
ICCAD
Altan Odabasioglu, Mustafa Celik, Lawrence T. Pileggi
1997 A* conf
SPIE: Sparse Partial Inductance Extraction.
DAC
Zhijiang He, Mustafa Celik, Lawrence T. Pileggi
1997 J jnl
Simulation of multiconductor transmission lines using Krylov subspace order-reduction techniques.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst.
Mustafa Celik, Andreas C. Cangellaris
1996 A conf
A general dispersive multiconductor transmission line model for interconnect simulation in SPICE.
ICCAD
Mustafa Celik, Andreas C. Cangellaris