Mustafa Badaroglu

40 papers A* 4A 4C 2Journal 17Unranked 12

Year	Rank	Type	Title / Venue / Authors
2022	—	`ed.`	Proceedings of the 24th ACM/IEEE Workshop on System Level Interconnect Pathfinding, SLIP 2022, San Diego, California, 3 November 2022 SLIP Mustafa Badaroglu, Shantanu Dutt
2022	—	`conf`	System-Level Simulation of Electromigration in a 3 nm CMOS Power Delivery Network: The Effect of Grid Redundancy, Metallization Stack and Standard-Cell Currents. IRPS Houman Zahedmanesh, Ivan Ciofi, Odysseas Zografos, Kristof Croes, Mustafa Badaroglu
2021	—	`conf`	A Novel System-Level Physics-Based Electromigration Modelling Framework: Application to the Power Delivery Network. SLIP Houman Zahedmanesh, Ivan Ciofi, Odysseas Zografos, Mustafa Badaroglu, Kristof Croes
2020	—	`conf`	Outlook of device and assembly technologies enabling high-performance mobile computing: IRDS view (invited). SLIP Mustafa Badaroglu
2018	J	`jnl`	Interconnect-Aware Technology and Design Co-Optimization for the 5-nm Technology and Beyond. J. Low Power Electron. Mustafa Badaroglu
2018	J	`jnl`	Internet-of-Things and big data for smarter healthcare: From device to architecture, applications and analytics. Future Gener. Comput. Syst. Farshad Firouzi, Amir M. Rahmani, Kunal Mankodiya, Mustafa Badaroglu, Geoff V. Merrett, P. Wong, Bahar J. Farahani
2018	J	`jnl`	Towards fog-driven IoT eHealth: Promises and challenges of IoT in medicine and healthcare. Future Gener. Comput. Syst. Bahar J. Farahani, Farshad Firouzi, Victor I. Chang, Mustafa Badaroglu, Nicholas Constant, Kunal Mankodiya
2017	—	`conf`	Investigation of electrically gate-all-around hexagonal nanowire FET (HexFET) architecture for 5 nm node logic and SRAM applications. ESSDERC Jeffrey A. Smith, Kai Ni, Ram Krishna Ghosh, Jeff Xu, Mustafa Badaroglu, P. R. Chidi Chidambaram, Suman Datta
2017	—	`conf`	PPAC scaling enablement for 5nm mobile SoC technology. ESSDERC Mustafa Badaroglu, Jeff Xu, John Zhu, Da Yang, Jerry Bao, Seung Chul Song, Peijie Feng, Romain Ritzenthaler, Hans Mertens, Geert Eneman, Naoto Horiguchi, Jeffrey Smith, Suman Datta, David Kohen, Po-Wen Chan, Keagan Chen, P. R. Chidi Chidambaram
2017	J	`jnl`	Sustaining Moore's Law with 3D Chips. Computer Erik P. DeBenedictis, Mustafa Badaroglu, An Chen, Thomas M. Conte, Paolo A. Gargini
2016	A	`conf`	Interconnect-aware device targeting from PPA perspective. ICCAD Mustafa Badaroglu, Jeff Xu
2016	—	`conf`	Unified Technology Optimization Platform using Integrated Analysis (UTOPIA) for holistic technology, design and system co-optimization at <= 7nm nodes. VLSI Circuits Seung Chul Song, J. Xu, D. Yang, K. Rim, P. Feng, Jerry Bao, J. Zhu, Joseph Wang, G. Nallapati, Mustafa Badaroglu, Praneeth Narayanasetti, B. Bucki, Jeff Fischer, Geoffrey Yeap
2015	—	`conf`	Holistic technology optimization and key enablers for 7nm mobile SoC. VLSIC Seung Chul Song, J. Xu, N. N. Mojumder, K. Rim, D. Yang, Jerry Bao, J. Zhu, Joseph Wang, Mustafa Badaroglu, V. Machkaoutsan, Praneeth Narayanasetti, B. Bucki, Jeff Fischer, Geoffrey Yeap
2014	C	`conf`	More Moore landscape for system readiness - ITRS2.0 requirements. ICCD Mustafa Badaroglu, Kwok Ng, Mehdi Salmani Jelodar, Sunggeun Kim, Gerhard Klimeck, Chorng-Ping Chang, Charles Cheung, Yuzo Fukuzaki
2013	A*	`conf`	TEASE: a systematic analysis framework for early evaluation of FinFET-based advanced technology nodes. DAC Arindam Mallik, Paul Zuber, Tsung-Te Liu, Bharani Chava, Bhavana Ballal, Pablo Royer Del Bario, Rogier Baert, Kris Croes, Julien Ryckaert, Mustafa Badaroglu, Abdelkarim Mercha, Diederik Verkest
2010	J	`jnl`	A Cascadable Random Neural Network Chip with Reconfigurable Topology. Comput. J. Mustafa Badaroglu, Ugur Halici, Isik Aybay, Cuneyt Cerkez
2008	A	`conf`	Calibration of Integrated CMOS Hall Sensors Using Coil-on-Chip in ATE Environment. DATE Mustafa Badaroglu, Guy Decabooter, Francois Laulanet, Olivier Charlier
2007	J	`jnl`	A CMOS Ultra-Wideband Receiver for Low Data-Rate Communication. IEEE J. Solid State Circuits Julien Ryckaert, Marian Verhelst, Mustafa Badaroglu, Stefano D'Amico, Vincent De Heyn, Claude Desset, Pierluigi Nuzzo, Bart van Poucke, Piet Wambacq, Andrea Baschirotto, Wim Dehaene, Geert Van der Plas
2007	—	`conf`	Optimized Signal Acquisition for Low-Complexity and Low-Power IR-UWB Transceivers. VTC Spring Claude Desset, Mustafa Badaroglu, Julien Ryckaert, Bart van Poucke
2007	C	`conf`	Scalable Gate-Level Models for Power and Timing Analysis. ISCAS Mustafa Badaroglu, Geert Van der Plas, Piet Wambacq, Stéphane Donnay, Georges G. E. Gielen, Hugo De Man
2006	—	`conf`	A 16mA UWB 3-to-5GHz 20Mpulses/s Quadrature Analog Correlation Receiver in 0.18µm CMOS. ISSCC Julien Ryckaert, Mustafa Badaroglu, Vincent De Heyn, Geert Van der Plas, Pierluigi Nuzzo, Andrea Baschirotto, Stefano D'Amico, Claude Desset, Hans Suys, Michael Libois, Bart van Poucke, Piet Wambacq, Bert Gyselinckx
2006	J	`jnl`	Analog-Digital Partitioning for Low-Power UWB Impulse Radios under CMOS Scaling. EURASIP J. Wirel. Commun. Netw. Mustafa Badaroglu, Claude Desset, Julien Ryckaert, Vincent De Heyn, Geert Van der Plas, Piet Wambacq, Bart van Poucke
2006	J	`jnl`	Clock-skew-optimization methodology for substrate-noise reduction with supply-current folding. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. Mustafa Badaroglu, Kris Tiri, Geert Van der Plas, Piet Wambacq, Ingrid Verbauwhede, Stéphane Donnay, Georges G. E. Gielen, Hugo De Man
2006	J	`jnl`	Evolution of substrate noise generation mechanisms with CMOS technology scaling. IEEE Trans. Circuits Syst. I Regul. Pap. Mustafa Badaroglu, Piet Wambacq, Geert Van der Plas, Stéphane Donnay, Georges G. E. Gielen, Hugo J. De Man
2006	J	`jnl`	Modeling of Substrate Noise Generation, Isolation, and Impact for an LC-VCO and a Digital Modem on a Lightly-Doped Substrate. IEEE J. Solid State Circuits Charlotte Soens, Geert Van der Plas, Mustafa Badaroglu, Piet Wambacq, Stéphane Donnay, Yves Rolain, Maarten Kuijk
2006	J	`jnl`	SWAN: high-level simulation methodology for digital substrate noise generation. IEEE Trans. Very Large Scale Integr. Syst. Mustafa Badaroglu, Geert Van der Plas, Piet Wambacq, Stéphane Donnay, Georges G. E. Gielen, Hugo De Man
2005	J	`jnl`	Digital ground bounce reduction by supply current shaping and clock frequency Modulation. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. Mustafa Badaroglu, Piet Wambacq, Geert Van der Plas, Stéphane Donnay, Georges G. E. Gielen, Hugo De Man
2005	J	`jnl`	Ultra-wide-band transmitter for low-power wireless body area networks: design and evaluation. IEEE Trans. Circuits Syst. I Regul. Pap. Julien Ryckaert, Claude Desset, Andrew Fort, Mustafa Badaroglu, Vincent De Heyn, Piet Wambacq, Geert Van der Plas, Stéphane Donnay, Bart van Poucke, Bert Gyselinckx
2004	A	`conf`	Digital Ground Bounce Reduction by Phase Modulation of the Clock. DATE Mustafa Badaroglu, Piet Wambacq, Geert Van der Plas, Stéphane Donnay, Georges G. E. Gielen, Hugo De Man
2004	J	`jnl`	Digital circuit capacitance and switching analysis for ground bounce in ICs with a high-ohmic substrate. IEEE J. Solid State Circuits Mustafa Badaroglu, Geert Van der Plas, Piet Wambacq, Lakshmanan Balasubramanian, Kris Tiri, Ingrid Verbauwhede, Stéphane Donnay, Georges G. E. Gielen, Hugo J. De Man
2004	A*	`conf`	High-level simulation of substrate noise in high-ohmic substrates with interconnect and supply effects. DAC Geert Van der Plas, Mustafa Badaroglu, Gerd Vandersteen, Petr Dobrovolný, Piet Wambacq, Stéphane Donnay, Georges G. E. Gielen, Hugo De Man
2004	—	`conf`	Impact of technology scaling on substrate noise generation mechanisms [mixed signal ICs]. CICC Mustafa Badaroglu, Piet Wambacq, Geert Van der Plas, Stéphane Donnay, Georges G. E. Gielen, Hugo De Man
2003	—	`conf`	Digital circuit capacitance and switching analysis for ground bounce in ICs with a high-ohmic substrate. ESSCIRC Mustafa Badaroglu, Lakshmanan Balasubramanian, Kris Tiri, Vincent Gravot, Piet Wambacq, Geert Van der Plas, Stéphane Donnay, Georges G. E. Gielen, Hugo De Man
2003	J	`jnl`	Modeling and experimental verification of substrate noise generation in a 220-Kgates WLAN system-on-chip with multiple supplies. IEEE J. Solid State Circuits Mustafa Badaroglu, Stéphane Donnay, Hugo J. De Man, Yann A. Zinzius, Georges G. E. Gielen, Willy Sansen, Tony Fondén, Svante Signell
2002	A*	`conf`	Clock tree optimization in synchronous CMOS digital circuits for substrate noise reduction using folding of supply current transients. DAC Mustafa Badaroglu, Kris Tiri, Stéphane Donnay, Piet Wambacq, Hugo De Man, Ingrid Verbauwhede, Georges G. E. Gielen
2002	J	`jnl`	Methodology and experimental verification for substrate noise reduction in CMOS mixed-signal ICs with synchronous digital circuits. IEEE J. Solid State Circuits Mustafa Badaroglu, Marc van Heijningen, Vincent Gravot, John Compiet, Stéphane Donnay, Georges G. E. Gielen, Hugo J. De Man
2002	J	`jnl`	Substrate noise generation in complex digital systems: efficient modeling and simulation methodology and experimental verification. IEEE J. Solid State Circuits Marc van Heijningen, Mustafa Badaroglu, Stéphane Donnay, Georges G. E. Gielen, Hugo J. De Man
2001	A	`conf`	High-level simulation of substrate noise generation from large digital circuits with multiple supplies. DATE Mustafa Badaroglu, Marc van Heijningen, Vincent Gravot, Stéphane Donnay, Hugo De Man, Georges G. E. Gielen, Marc Engels, Ivo Bolsens
2000	A*	`conf`	High-level simulation of substrate noise generation including power supply noise coupling. DAC Marc van Heijningen, Mustafa Badaroglu, Stéphane Donnay, Marc Engels, Ivo Bolsens
1999	—	`conf`	BANDIT: embedding analog-to-digital converters on digital telecom ASICs. ICECS Stéphane Donnay, Marc van Heijningen, Mustafa Badaroglu, Wim Diels, Marc Engels, Ivo Bolsens, Yann A. Zinzius, Georges G. E. Gielen, Willy Sansen, Tony Fondén, Svante Signell