| Year | Rank | Type | Title / Venue / Authors |
|---|---|---|---|
| 2024 | J | jnl |
CoRR
|
| 2024 | J | jnl |
CoRR
|
| 2022 | C | conf |
IECON
|
| 2018 | — | conf |
SIU
|
| 2016 | J | jnl |
IEEE Trans. Ind. Electron.
|
| 2010 | C | conf |
ISCAS
|
| 2008 | — | conf |
Delay insensitivity verification of bit-level pipelined systolic arrays in dual-rail treshold logic.
ICECS
|
| 2008 | C | conf |
DSD
|
| 2007 | C | conf |
ISCAS
|
| 2006 | J | jnl |
Microelectron. J.
|
| 2004 | C | conf |
DSD
|
| 2004 | — | conf |
ISCAS (2)
|
| 2004 | — | conf |
ICECS
|
| 2004 | — | conf |
ISCAS (2)
|
| 2003 | — | conf |
VLSI
|
| 1999 | — | conf |
ISSPA
|