Muralidhar Pullakandam

18 papers Misc 1Journal 11Unranked 6
YearRankTypeTitle / Venue / Authors
2026 J jnl
Elevating efficiency: Field-Programmable Gate Array Powered Acceleration of MobileNet V1 with patchwise innovation, double buffering, and Singular Value Decomposition Optimization.
Eng. Appl. Artif. Intell.
Rama Muni Reddy Yanamala, Muralidhar Pullakandam, Rayappa David Amar Raj
2026 J jnl
Fast Convolutional Neural Network based coding unit size prediction in HEVC.
Multidimens. Syst. Signal Process.
Karthik Sairam Sanagavarapu, Muralidhar Pullakandam
2026 Misc conf
IncepLite: An FPGA Based InceptionNet Accelerator for ECG Classification at Edge Devices.
VLSID
Anju Yajjala, Muralidhar Pullakandam, Gopala Krishna Thota
2026 J jnl
Scalable SoC Architecture for Parallel-Pixel Classification of Hyperspectral Images Using Weighted-Summation Kernel SVM.
Concurr. Comput. Pract. Exp.
B. B. Shabarinath, Muralidhar Pullakandam
2025 J jnl
Embedded Hardware-Efficient FPGA Architecture for SVM Learning and Inference.
IEEE Access
B. B. Shabarinath, Muralidhar Pullakandam
2025 J jnl
FPGA-accelerated hybrid CNN-LSTM system for efficient EEG-based drowsiness recognition.
J. Supercomput.
Rama Muni Reddy Yanamala, Muralidhar Pullakandam
2025 J jnl
Low Latency Multikernel Polar Codes Using Approximate Processing Element.
Int. J. Circuit Theory Appl.
Nandini Jali, Muralidhar Pullakandam, Sreehari Rao Patri
2024 J jnl
Empowering edge devices: FPGA-based 16-bit fixed-point accelerator with SVD for CNN on 32-bit memory-limited systems.
Int. J. Circuit Theory Appl.
Rama Muni Reddy Yanamala, Muralidhar Pullakandam
2024 J jnl
High-Speed Power Allocation in NOMA System Using FPGA-Based DNN.
J. Circuits Syst. Comput.
Rama Muni Reddy Yanamala, Muralidhar Pullakandam
2023 J jnl
A high-speed reusable quantized hardware accelerator design for CNN on constrained edge device.
Des. Autom. Embed. Syst.
Rama Muni Reddy Yanamala, Muralidhar Pullakandam
2023 — conf
Advanced Powerplanning Strategy Utilising Aprisa - Image Edge Detector.
ICCCNT
Roshan Agarwal, Muralidhar Pullakandam, Gopinath Agrahara, Amarnadh Akavarapu
2023 — conf
Pneumonia Detection Using Transfer Learning And Hardware Implementation in Edge TPU.
ICCCNT
Sujay Kumar Mandal, Muralidhar Pullakandam, Rama Muni Reddy Yanamala
2023 J jnl
SoC-based real-time SVM classification with integrated training using HLS and PYNQ.
Microprocess. Microsystems
B. B. Shabarinath, Muralidhar Pullakandam
2022 — conf
An Efficient Configurable Hardware Accelerator Design for CNN on Low Memory 32-Bit Edge Device.
iSES
Rama Muni Reddy Yanamala, Muralidhar Pullakandam
2022 — conf
Efficient successive cancellation decoder architecture for multi-kernel polar codes.
iSES
Nandini Jali, Muralidhar Pullakandam, Sreehari Rao Patri
2022 — conf
The chaotic-based challenge feed mechanism for Arbiter Physical Unclonable Functions (APUFs) with enhanced reliability in IoT security.
iSES
Raveendra Podeti, Sreehari Rao Patri, Muralidhar Pullakandam
2021 J jnl
Highly reliable XoR Feed Arbiter Physical Unclonable Function (XFAPUF) in 180 nm process for IoT security.
Microprocess. Microsystems
Raveendra Podeti, Sreehari Rao Patri, Muralidhar Pullakandam
2021 — conf
ReOPUF: Relaxation Oscillator Physical Unclonable Function for Reliable Key Generation in IoT Security.
IFIPIoT
Raveendra Podeti, Srihari Rao Patri, Srinivas Katkoori, Muralidhar Pullakandam