Muralidaran Vijayaraghavan

24 papers A* 1A 1B 3C 9Journal 8Unranked 1
YearRankTypeTitle / Venue / Authors
2018 A* conf
Constructing a Weak Memory Model.
ISCA
Sizhuo Zhang, Muralidaran Vijayaraghavan, Andrew Wright, Mehdi Alipour, Arvind
2018 J jnl
Constructing a Weak Memory Model.
CoRR
Sizhuo Zhang, Muralidaran Vijayaraghavan, Andrew Wright, Mehdi Alipour, Arvind
2017 J jnl
An Operational Framework for Specifying Memory Models using Instantaneous Instruction Execution.
CoRR
Sizhuo Zhang, Muralidaran Vijayaraghavan, Arvind
2017 J jnl
Kami: a platform for high-level parametric hardware specification and its modular verification.
Proc. ACM Program. Lang.
Joonwon Choi, Muralidaran Vijayaraghavan, Benjamin Sherman, Adam Chlipala, Arvind
2017 J jnl
Weak Memory Models with Matching Axiomatic and Operational Definitions.
CoRR
Sizhuo Zhang, Muralidaran Vijayaraghavan, Dan Lustig, Arvind
2017 B conf
Weak Memory Models: Balancing Definitional Simplicity and Implementation Flexibility.
PACT
Sizhuo Zhang, Muralidaran Vijayaraghavan, Arvind
2017 J jnl
Weak Memory Models: Balancing Definitional Simplicity and Implementation Flexibility.
CoRR
Sizhuo Zhang, Muralidaran Vijayaraghavan, Arvind
2016 — —
Modular verification of hardware systems.
Muralidaran Vijayaraghavan
2016 J jnl
Taming Weak Memory Models.
CoRR
Sizhuo Zhang, Arvind, Muralidaran Vijayaraghavan
2015 J jnl
A Proof of Correctness for the Tardis Cache Coherence Protocol.
CoRR
Xiangyao Yu, Muralidaran Vijayaraghavan, Srinivas Devadas
2015 — conf
Modular Deductive Verification of Multiprocessor Hardware Designs.
CAV (2)
Muralidaran Vijayaraghavan, Adam Chlipala, Arvind, Nirav Dave
2014 C conf
A new synthesis procedure for atomic rules containing multi-cycle function blocks.
MEMOCODE
Michal Karczmarek, Arvind, Muralidaran Vijayaraghavan
2013 C conf
Modular compilation of guarded atomic actions.
MEMOCODE
Muralidaran Vijayaraghavan, Nirav Dave, Arvind
2012 C conf
A general technique for deterministic model-cycle-level debugging.
MEMOCODE
Asif Khan, Muralidaran Vijayaraghavan, Arvind
2012 B conf
Fast and cycle-accurate modeling of a multicore processor.
ISPASS
Asif Khan, Muralidaran Vijayaraghavan, Silas Boyd-Wickizer, Arvind
2010 C conf
Design contest overview: Combined architecture for network stream categorization and intrusion detection (CANSCID).
MEMOCODE
Michael Pellauer, Abhinav Agarwal, Asif Khan, Man Cheuk Ng, Muralidaran Vijayaraghavan, Forrest Brewer, Joel S. Emer
2009 J jnl
A-Port Networks: Preserving the Timed Behavior of Synchronous Systems for Modeling on FPGAs.
ACM Trans. Reconfigurable Technol. Syst.
Michael Pellauer, Muralidaran Vijayaraghavan, Michael Adler, Arvind, Joel S. Emer
2009 C conf
Bounded Dataflow Networks and Latency-Insensitive circuits.
MEMOCODE
Muralidaran Vijayaraghavan, Arvind
2009 C conf
Implementing a fast cartesian-polar matrix interpolator.
MEMOCODE
Abhinav Agarwal, Nirav Dave, Kermin Fleming, Asif Khan, Myron King, Man Cheuk Ng, Muralidaran Vijayaraghavan
2008 A conf
A-Ports: an efficient abstraction for cycle-accurate performance models on FPGAs.
FPGA
Michael Pellauer, Muralidaran Vijayaraghavan, Michael Adler, Arvind, Joel S. Emer
2008 C conf
High-throughput Pipelined Mergesort.
MEMOCODE
Kermin Fleming, Myron King, Man Cheuk Ng, Asif Khan, Muralidaran Vijayaraghavan
2008 B conf
Quick Performance Models Quickly: Closely-Coupled Partitioned Simulation on FPGAs.
ISPASS
Michael Pellauer, Muralidaran Vijayaraghavan, Michael Adler, Arvind, Joel S. Emer
2007 C conf
From WiFi to WiMAX: Techniques for High-Level IP Reuse across Different OFDM Protocols.
MEMOCODE
Man Cheuk Ng, Muralidaran Vijayaraghavan, Nirav Dave, Arvind, Gopal Raghavan, Jamey Hicks
2007 C conf
Hardware Acceleration of Matrix Multiplication on a Xilinx FPGA.
MEMOCODE
Nirav Dave, Kermin Fleming, Myron King, Michael Pellauer, Muralidaran Vijayaraghavan