Murali Jayapala

44 papers A 3B 2C 1Misc 3Journal 14Unranked 21

Year	Rank	Type	Title / Venue / Authors
2024	—	`conf`	Microplastic Discrimination with Hyperspectral Microscopy. WHISPERS Carolina Blanch Perez del Notario, Aala Azari, Murali Jayapala, Andy Lambrechts
2024	—	`conf`	Multispectral Snapshot Microscopy as an Exposure Assessment Tool. WHISPERS Carolina Blanch Perez del Notario, Amir Asadollahi, Pieter Bertier, Murali Jayapala
2023	—	`conf`	Band Relevance Study of SWIR Hyperspectral Imaging for Material Recycling and Reuse. WHISPERS Carolina Blanch Perez del Notario, Steven Thijs, Murali Jayapala
2023	—	`conf`	Drone-Based Corrosion Detection on High-Voltage Transmission Towers Using Hyperspectral Imaging. WHISPERS Michiel Vlaminck, Zakaria Bnoulkacem, Gonzalo Luzardo, Hamed Zivari Adab, Zohreh Zahiri, Bikram Koirala, Frédéric Mangialetto, Irid Bufi, Ljiljana Platisa, Murali Jayapala, Paul Scheunders, Hiep Luong
2023	J	`jnl`	Intra-operative Brain Tumor Detection with Deep Learning-Optimized Hyperspectral Imaging. CoRR Tommaso Giannantonio, Anna Alperovich, Piercosimo Semeraro, Manfredo Atzori, Xiaohan Zhang, Christoph Hauger, Alexander Freytag, Siri Luthman, Roeland Vandebriel, Murali Jayapala, Lien Solie, Steven De Vleeschouwer
2019	J	`jnl`	Graph and Rank Regularized Matrix Recovery for Snapshot Spectral Image Demosaicing. IEEE Trans. Computational Imaging Grigorios Tsagkatakis, Maarten Bloemen, Bert Geelen, Murali Jayapala, Panagiotis Tsakalides
2016	—	`conf`	Characterization of VNIR Hyperspectral Sensors with Monolithically Integrated Optical Filters. IMSE Prashant Agrawal, Klaas Tack, Bert Geelen, Bart Masschelein, Pablo Mateo Aranda Moran, Andy Lambrechts, Murali Jayapala
2016	—	`conf`	Non-negative Matrix Completion for the Enhancement of Snapshot Mosaic Multispectral Imagery. IMSE Grigorios Tsagkatakis, Murali Jayapala, Bert Geelen, Panagiotis Tsakalides
2011	—	`conf`	Automated architecture exploration for low energy reconfigurable AGU. ISOCC Ittetsu Taniguchi, Murali Jayapala, Praveen Raghavan, Francky Catthoor, Keishi Sakanushi, Yoshinori Takeuchi, Masaharu Imai
2009	C	`conf`	Compilation Technique for Loop Overhead Minimization. DSD Nikolas Kroupis, Praveen Raghavan, Murali Jayapala, Francky Catthoor, Dimitrios Soudris
2009	J	`jnl`	Distributed Loop Controller for Multithreading in Unithreaded ILP Architectures. IEEE Trans. Computers Praveen Raghavan, Andy Lambrechts, Murali Jayapala, Francky Catthoor, Diederik Verkest
2009	J	`jnl`	EMPIRE: Empirical power/area/timing models for register files. Microprocess. Microsystems Praveen Raghavan, Andy Lambrechts, Murali Jayapala, Francky Catthoor, Diederik Verkest
2009	J	`jnl`	Interconnect Exploration for Energy Versus Performance Tradeoffs for Coarse Grained Reconfigurable Architectures. IEEE Trans. Very Large Scale Integr. Syst. Andy Lambrechts, Praveen Raghavan, Murali Jayapala, Bingfeng Mei, Francky Catthoor, Diederik Verkest
2009	J	`jnl`	Locality optimization in a compiler for wireless applications. Des. Autom. Embed. Syst. Javed Absar, Praveen Raghavan, Andy Lambrechts, Min Li, Murali Jayapala, Francky Catthoor
2009	J	`jnl`	Playing the trade-off game: Architecture exploration using Coffeee. ACM Trans. Design Autom. Electr. Syst. Praveen Raghavan, Murali Jayapala, Andy Lambrechts, Javed Absar, Francky Catthoor
2009	J	`jnl`	Reconfigurable AGU: An Address Generation Unit Based on Address Calculation Pattern for Low Energy and High Performance Embedded Processors. IEICE Trans. Fundam. Electron. Commun. Comput. Sci. Ittetsu Taniguchi, Praveen Raghavan, Murali Jayapala, Francky Catthoor, Yoshinori Takeuchi, Masaharu Imai
2009	—	`conf`	Systematic architecture exploration based on optimistic cycle estimation for low energy embedded processors. ASP-DAC Ittetsu Taniguchi, Murali Jayapala, Praveen Raghavan, Francky Catthoor, Keishi Sakanushi, Yoshinori Takeuchi, Masaharu Imai
2008	J	`jnl`	Address Generation Optimization for Embedded High-Performance Processors: A Survey. J. Signal Process. Syst. Guillermo Talavera, Murali Jayapala, Jordi Carrabina, Francky Catthoor
2008	—	`conf`	Coffee: COmpiler Framework for Energy-Aware Exploration. HiPEAC Praveen Raghavan, Andy Lambrechts, Javed Absar, Murali Jayapala, Francky Catthoor, Diederik Verkest
2008	J	`jnl`	Efficient Method to Generate an Energy Efficient Schedule Using Operation Shuffling. IEICE Trans. Fundam. Electron. Commun. Comput. Sci. Yuki Kobayashi, Murali Jayapala, Praveen Raghavan, Francky Catthoor, Masaharu Imai
2008	Misc	`conf`	Energy-Aware Interconnect Optimization for a Coarse Grained Reconfigurable Processor. VLSI Design Andy Lambrechts, Praveen Raghavan, Murali Jayapala, Francky Catthoor, Diederik Verkest
2008	—	`conf`	Operation shuffling over cycle boundaries for low energy L0 clustering. ASAP Yuki Kobayashi, Murali Jayapala, Praveen Raghavan, Francky Catthoor, Masaharu Imai
2007	—	`conf`	A Customized Cross-Bar for Data-Shuffling in Domain-Specific SIMD Processors. ARCS Praveen Raghavan, Satyakiran Munaga, Estela Rey Ramos, Andy Lambrechts, Murali Jayapala, Francky Catthoor, Diederik Verkest
2007	—	`conf`	Architectures and Circuits for Software-Defined Radios: Scaling and Scalability for Low Cost and Low Energy. ISSCC Liesbet Van der Perre, Bruno Bougard, Jan Craninckx, Wim Dehaene, Lieven Hollevoet, Murali Jayapala, Pol Marchal, Miguel Miranda, Praveen Raghavan, Thomas Schuster, Piet Wambacq, Francky Catthoor, Peter Vanbekbergen
2007	Misc	`conf`	Locality optimization in wireless applications. CODES+ISSS Javed Absar, Min Li, Praveen Raghavan, Andy Lambrechts, Murali Jayapala, Arnout Vandecappelle, Francky Catthoor
2007	J	`jnl`	Methodology for operation shuffling and L0 cluster generation for low energy heterogeneous VLIW processors. ACM Trans. Design Autom. Electr. Syst. Yuki Kobayashi, Murali Jayapala, Praveen Raghavan, Francky Catthoor, Masaharu Imai
2007	—	`conf`	Semi Custom Design: A Case Study on SIMD Shufflers. PATMOS Praveen Raghavan, Nandhavel Sethubalasubramanian, Satyakiran Munaga, Estela Rey Ramos, Murali Jayapala, Oliver Weiss, Francky Catthoor, Diederik Verkest
2007	A	`conf`	Very wide register: an asymmetric register file organization for low power embedded processors. DATE Praveen Raghavan, Andy Lambrechts, Murali Jayapala, Francky Catthoor, Diederik Verkest, Henk Corporaal
2006	A	`conf`	Distributed loop controller architecture for multi-threading in uni-threaded VLIW processors. DATE Praveen Raghavan, Andy Lambrechts, Murali Jayapala, Francky Catthoor, Diederik Verkest
2006	—	`conf`	Instruction Transfer And Storage Exploration for Low Energy VLIWs. SiPS Tom Vander Aa, Murali Jayapala, Henk Corporaal, Francky Catthoor, Geert Deconinck
2005	J	`jnl`	Clustered Loop Buffer Organization for Low Energy VLIW Embedded Processors. IEEE Trans. Computers Murali Jayapala, Francisco Barat, Tom Vander Aa, Francky Catthoor, Henk Corporaal, Geert Deconinck
2005	J	`jnl`	Instruction buffering exploration for low energy embedded processors. J. Embed. Comput. Tom Vander Aa, Murali Jayapala, Francisco Barat, Geert Deconinck, Rudy Lauwereins, Henk Corporaal, Francky Catthoor
2005	—	`conf`	Operation Shuffling for Low Energy L0 Cluster Generation on Heterogeneous VLIW Processors. ESTIMedia Yuki Kobayashi, Murali Jayapala, Praveen Raghavan, Francky Catthoor, Masaharu Imai
2005	—	`conf`	Power Breakdown Analysis for a Heterogeneous NoC Platform Running a Video Application. ASAP Andy Lambrechts, Praveen Raghavan, Anthony Leroy, Guillermo Talavera, Tom Vander Aa, Murali Jayapala, Francky Catthoor, Diederik Verkest, Geert Deconinck, Henk Corporaal, Frédéric Robert, Jordi Carrabina
2004	A	`conf`	Design Style Case Study for Embedded Multi Media Compute Nodes. RTSS Andy Lambrechts, Tom Vander Aa, Murali Jayapala, Guillermo Talavera, Anthony Leroy, Adelina Shickova, Francisco Barat, Bingfeng Mei, Francky Catthoor, Diederik Verkest, Geert Deconinck, Henk Corporaal, Frédéric Robert, Jordi Carrabina Bordoll
2004	—	`conf`	Instruction buffering exploration for low energy VLIWs with instruction clusters. ASP-DAC Tom Vander Aa, Murali Jayapala, Francisco Barat, Geert Deconinck, Rudy Lauwereins, Francky Catthoor, Henk Corporaal
2004	—	`conf`	L0 Cluster Synthesis and Operation Shuffling. PATMOS Murali Jayapala, Tom Vander Aa, Francisco Barat, Francky Catthoor, Henk Corporaal, Geert Deconinck
2004	Misc	`conf`	L0 buffer energy optimization through scheduling and exploration. SAC Murali Jayapala, Tom Vander Aa, Francisco Barat, Geert Deconinck, Francky Catthoor, Henk Corporaal
2003	—	`conf`	Instruction Buffering Exploration for Low Energy Embedded Processors. PATMOS Tom Vander Aa, Murali Jayapala, Francisco Barat, Geert Deconinck, Rudy Lauwereins, Henk Corporaal, Francky Catthoor
2003	B	`conf`	Low Power Coarse-Grained Reconfigurable Instruction Set Processor. FPL Francisco Barat, Murali Jayapala, Tom Vander Aa, Rudy Lauwereins, Geert Deconinck, Henk Corporaal
2002	—	`conf`	A Low Energy Clustered Instruction Memory Hierarchy for Long Instruction Word Processors. PATMOS Murali Jayapala, Francisco Barat, Pieter Op de Beeck, Francky Catthoor, Geert Deconinck, Henk Corporaal
2002	J	`jnl`	Matador: An Exploration Environment for System-Design. J. Circuits Syst. Comput. Paul Marchal, Murali Jayapala, Samuel Xavier de Souza, Peng Yang, Francky Catthoor, Geert Deconinck
2002	—	`conf`	Software Pipelining for Coarse-Grained Reconfigurable Instruction Set Processors. ASP-DAC/VLSI Design Francisco Barat, Murali Jayapala, Pieter Op de Beeck, Geert Deconinck
2001	B	`conf`	CRISP: A Template for Reconfigurable Instruction Set Processors. FPL Pieter Op de Beeck, Francisco Barat, Murali Jayapala, Rudy Lauwereins