Munehiro Matsuura

51 papers A* 2A 1B 2C 6Journal 18Unranked 22
YearRankTypeTitle / Venue / Authors
2016 J jnl
An Update Method for a Low Power Cam Emulator Using an LUT Cascade Based on an EVMDD (
J. Multiple Valued Log. Soft Comput.
Hiroki Nakahara, Tsutomu Sasao, Munehiro Matsuura, Hisashi Iwamoto
2016 J jnl
LUT Cascades Based on Edge-Valued Multi-Valued Decision Diagrams: Application to Packet Classification.
IEEE J. Emerg. Sel. Topics Circuits Syst.
Hiroki Nakahara, Tsutomu Sasao, Hisashi Iwamoto, Munehiro Matsuura
2015 J jnl
A Memory-Based IPv6 Lookup Architecture Using Parallel Index Generation Units.
IEICE Trans. Inf. Syst.
Hiroki Nakahara, Tsutomu Sasao, Munehiro Matsuura, Hisashi Iwamoto, Yasuhiro Terao
2014 J jnl
A Heterogeneous Multi-valued Decision Diagram Machine for Encoded Characteristic Function for Non-zero Outputs.
J. Multiple Valued Log. Soft Comput.
Hiroki Nakahara, Tsutomu Sasao, Munehiro Matsuura
2014 J jnl
A Packet Classifier Based on Prefetching EVMDD (
IEICE Trans. Inf. Syst.
Hiroki Nakahara, Tsutomu Sasao, Munehiro Matsuura
2014 — conf
An Update Method for a CAM Emulator Using an LUT Cascade Based on an EVMDD (K).
ISMVL
Hiroki Nakahara, Tsutomu Sasao, Munehiro Matsuura
2013 — conf
A Machine to Evaluate Decomposed Multi-Terminal Multi-Valued Decision Diagrams for Characteristic Functions.
ISMVL
Hiroki Nakahara, Tsutomu Sasao, Munehiro Matsuura
2013 J jnl
A Virus Scanning Engine Using an MPU and an IGU Based on Row-Shift Decomposition.
IEICE Trans. Inf. Syst.
Hiroki Nakahara, Tsutomu Sasao, Munehiro Matsuura
2013 B conf
A packet classifier using LUT cascades based on EVMDDS (k).
FPL
Hiroki Nakahara, Tsutomu Sasao, Munehiro Matsuura
2013 — conf
An Architecture for IPv6 Lookup Using Parallel Index Generation Units.
ARC
Hiroki Nakahara, Tsutomu Sasao, Munehiro Matsuura
2012 J jnl
A Comparison of Multi-Valued and Heterogeneous Decision Diagram Machines.
J. Multiple Valued Log. Soft Comput.
Hiroki Nakahara, Tsutomu Sasao, Munehiro Matsuura
2012 J jnl
A Design Method of a Regular Expression Matching Circuit Based on Decomposed Automaton.
IEICE Trans. Inf. Syst.
Hiroki Nakahara, Tsutomu Sasao, Munehiro Matsuura
2012 — conf
A Low-Cost and High-Performance Virus Scanning Engine Using a Binary CAM Emulator and an MPU.
ARC
Hiroki Nakahara, Tsutomu Sasao, Munehiro Matsuura
2012 J jnl
A regular expression matching circuit: Decomposed non-deterministic realization with prefix sharing and multi-character transition.
Microprocess. Microsystems
Hiroki Nakahara, Tsutomu Sasao, Munehiro Matsuura
2012 — conf
Multi-terminal Multi-valued Decision Diagrams for Characteristic Function Representing Cluster Decomposition.
ISMVL
Hiroki Nakahara, Tsutomu Sasao, Munehiro Matsuura
2011 — conf
A Comparison of Heterogeneous Multi-valued Decision Diagram Machines for Multiple-Output Logic Functions.
ISMVL
Hiroki Nakahara, Tsutomu Sasao, Munehiro Matsuura
2011 — conf
A Regular Expression Matching Circuit Based on a Decomposed Automaton.
ARC
Hiroki Nakahara, Tsutomu Sasao, Munehiro Matsuura
2010 — conf
A Comparison of Architectures for Various Decision Diagram Machines.
ISMVL
Hiroki Nakahara, Tsutomu Sasao, Munehiro Matsuura
2010 C conf
A Packet Classifier Using a Parallel Branching Program Machine.
DSD
Hiroki Nakahara, Tsutomu Sasao, Munehiro Matsuura
2010 J jnl
A Parallel Branching Program Machine for Sequential Circuits: Implementation and Evaluation.
IEICE Trans. Inf. Syst.
Hiroki Nakahara, Tsutomu Sasao, Munehiro Matsuura, Yoshifumi Kawamura
2010 J jnl
A Quaternary Decision Diagram Machine: Optimization of Its Code.
IEICE Trans. Inf. Syst.
Tsutomu Sasao, Hiroki Nakahara, Munehiro Matsuura, Yoshifumi Kawamura, Jon T. Butler
2010 C conf
A regular expression matching using non-deterministic finite automaton.
MEMOCODE
Hiroshi Nakahara, Tsutomu Sasao, Munehiro Matsuura
2009 — conf
A Parallel Branching Program Machine for Emulation of Sequential Circuits.
ARC
Hiroki Nakahara, Tsutomu Sasao, Munehiro Matsuura, Yoshifumi Kawamura
2009 — conf
A Quaternary Decision Diagram Machine and the Optimization of its Code.
ISMVL
Tsutomu Sasao, Hiroki Nakahara, Munehiro Matsuura, Yoshifumi Kawamura, Jon T. Butler
2009 B conf
A virus scanning engine using a parallel finite-input memory machine and MPUs.
FPL
Hiroki Nakahara, Tsutomu Sasao, Munehiro Matsuura, Yoshifumi Kawamura
2009 C conf
Representation of Incompletely Specified Index Generation Functions Using Minimal Number of Compound Variables.
DSD
Tsutomu Sasao, Takaaki Nakamura, Munehiro Matsuura
2009 C conf
The Parallel Sieve Method for a Virus Scanning Engine.
DSD
Hiroki Nakahara, Tsutomu Sasao, Munehiro Matsuura, Yoshifumi Kawamura
2007 A conf
A CAM Emulator Using Look-Up Table Cascades.
IPDPS
Hiroki Nakahara, Tsutomu Sasao, Munehiro Matsuura
2007 C conf
An Implementation of an Address Generator Using Hash Memories.
DSD
Tsutomu Sasao, Munehiro Matsuura
2007 J jnl
BDD Representation for Incompletely Specified Multiple-Output Logic Functions and Its Applications to the Design of LUT Cascades.
IEICE Trans. Fundam. Electron. Commun. Comput. Sci.
Munehiro Matsuura, Tsutomu Sasao
2007 J jnl
Design Methods for Binary to Decimal Converters Using Arithmetic Decompositions.
J. Multiple Valued Log. Soft Comput.
Yukihiro Iguchi, Tsutomu Sasao, Munehiro Matsuura
2007 J jnl
Design Methods of Radix Converters Using Arithmetic Decompositions.
IEICE Trans. Inf. Syst.
Yukihiro Iguchi, Tsutomu Sasao, Munehiro Matsuura
2007 — conf
On Designs of Radix Converters Using Arithmetic Decompositions--Binary to Decimal Converters--.
ISMVL
Yukihiro Iguchi, Tsutomu Sasao, Munehiro Matsuura
2006 J jnl
A PC-Based Logic Simulator Using a Look-Up Table Cascade Emulator.
IEICE Trans. Fundam. Electron. Commun. Comput. Sci.
Hiroki Nakahara, Tsutomu Sasao, Munehiro Matsuura
2006 — conf
A fast logic simulator using a look up table cascade emulator.
ASP-DAC
Hiroki Nakahara, Tsutomu Sasao, Munehiro Matsuura
2006 — conf
On Designs of Radix Converters Using Arithmetic Decompositions.
ISMVL
Yukihiro Iguchi, Tsutomu Sasao, Munehiro Matsuura
2005 J jnl
A Design Algorithm for Sequential Circuits Using LUT Rings.
IEICE Trans. Fundam. Electron. Commun. Comput. Sci.
Hiroki Nakahara, Tsutomu Sasao, Munehiro Matsuura
2005 J jnl
Average Path Length of Binary Decision Diagrams.
IEEE Trans. Computers
Jon T. Butler, Tsutomu Sasao, Munehiro Matsuura
2005 A* conf
BDD representation for incompletely specifiedvmultiple-output logic functions and its applications to functional decomposition.
DAC
Tsutomu Sasao, Munehiro Matsuura
2004 — conf
A Method to Evaluate Logic Functions in the Presence of Unknown Inputs Using LUT Cascades.
ISMVL
Yukihiro Iguchi, Tsutomu Sasao, Munehiro Matsuura
2004 A* conf
A method to decompose multiple-output logic functions.
DAC
Tsutomu Sasao, Munehiro Matsuura
2003 — conf
Evaluation of multiple-output logic functions using decision diagrams.
ASP-DAC
Yukihiro Iguchi, Tsutomu Sasao, Munehiro Matsuura
2002 J jnl
Bi-Partition of Shared Binary Decision Diagrams.
IEICE Trans. Fundam. Electron. Commun. Comput. Sci.
Munehiro Matsuura, Tsutomu Sasao, Jon T. Butler, Yukihiro Iguchi
2002 — conf
Comparison of Decision Diagrams for Multiple-Output Logic Functions.
IWLS
Tsutomu Sasao, Yukihiro Iguchi, Munehiro Matsuura
2002 — conf
Representations of Logic Functions Using QRMDDs.
ISMVL
Shinobu Nagayama, Tsutomu Sasao, Yukihiro Iguchi, Munehiro Matsuura
2001 C conf
Realization of Multiple-Output Functions by Reconfigurable Cascades.
ICCD
Yukihiro Iguchi, Tsutomu Sasao, Munehiro Matsuura
2000 — conf
A hardware simulation engine based on decision diagrams (short paper).
ASP-DAC
Yukihiro Iguchi, Tsutomu Sasao, Munehiro Matsuura, Atsumu Iseno
2000 — conf
Implementation of Multiple-Output Functions Using PQMDDs.
ISMVL
Yukihiro Iguchi, Tsutomu Sasao, Munehiro Matsuura
1999 — conf
Realization of Regular Ternary Logic Functions.
ASP-DAC
Yukihiro Iguchi, Munehiro Matsuura, Tsutomu Sasao, Atsumu Iseno
1997 — conf
On Decomposition of Kleene TDDs.
Asian Test Symposium
Yukihiro Iguchi, Tsutomu Sasao, Munehiro Matsuura
1997 — conf
On properties of Kleene TDDs.
ASP-DAC
Yukihiro Iguchi, Tsutomu Sasao, Munehiro Matsuura