Muhammad M. Khellah

74 papers A* 2A 5C 4Journal 31Unranked 32

Year	Rank	Type	Title / Venue / Authors
2023	—	`conf`	A 2.6 mV/b Resolution, 1.2 GHz Throughput, All-Digital Voltage Droop Monitor Using Coupled Ring Oscillators in Intel 4 CMOS. VLSI Technology and Circuits Charles Augustine, Pascal Meinerzhagen, Wootaek Lim, A. Veerabathini, M. Bright, K. Mojjada, Jim Tschanz, Muhammad M. Khellah, Vivek De
2021	J	`jnl`	A Back-Sampling Chain Technique for Accelerated Detection, Characterization, and Reconstruction of Radiation-Induced Transient Pulses. IEEE Trans. Very Large Scale Integr. Syst. Saurabh Kumar, Minki Cho, Luke R. Everson, Andres Malavasi, Dan Lake, Carlos Tokunaga, Muhammad M. Khellah, James W. Tschanz, Vivek De, Chris H. Kim
2021	J	`jnl`	Advances in Microprocessor Cache Architectures Over the Last 25 Years. IEEE Micro Ravi R. Iyer, Vivek De, Ramesh Illikkal, David A. Koufaty, Bhushan Chitlur, Andrew Herdrich, Muhammad M. Khellah, Fatih Hamzaoglu, Eric Karl
2021	—	`conf`	All-Digital Closed-Loop Unified Retention/Wake-Up Clamp in a 10nm 4-Core x86 IP. VLSI Circuits Charles Augustine, A. Afzal, U. Misgar, Abdullah A. Owahid, A. Raman, K. Subramanian, Feroze Merchant, James W. Tschanz, Muhammad M. Khellah
2020	—	`conf`	25.1 A Fully Synthesizable Distributed and Scalable All-Digital LDO in 10nm CMOS. ISSCC Suyoung Bang, Wootaek Lim, Charles Augustine, Andres Malavasi, Muhammad M. Khellah, James W. Tschanz, Vivek De
2020	—	`conf`	2X-Bandwidth Burst 6T-SRAM for Memory Bandwidth Limited Workloads. VLSI Circuits Charles Augustine, Somnath Paul, Turbo Majumder, James W. Tschanz, Muhammad M. Khellah, Vivek De
2020	—	`conf`	A 0.05pJ/Pixel 70fps FHD 1Meps Event-Driven Visual Data Processing Unit. VLSI Circuits Somnath Paul, Turbo Majumder, Charles Augustine, Andres F. Malavasi, S. Usirikayala, Raghavan Kumar, Jisna Kollikunnel, S. Chhabra, Satish Yada, M. L. Barajas, Carlos Ornelas, Dan Lake, Muhammad M. Khellah, Jim Tschanz, Vivek De
2020	J	`jnl`	An All-Digital, $V_{\mathrm{MAX}}$ -Compliant, Stable, and Scalable Distributed Charge Injection Scheme in 10-nm CMOS for Fast and Local Mitigation of Voltage Droop. IEEE J. Solid State Circuits Suyoung Bang, Minki Cho, Pascal Andreas Meinerzhagen, Andres Malavasi, Muhammad M. Khellah, James W. Tschanz, Vivek De
2020	—	`conf`	Low Swing and Column Multiplexed Bitline Techniques for Low-Vmin, Noise-Tolerant, High-Density, 1R1W 8T-Bitcell SRAM in 10nm FinFET CMOS. VLSI Circuits Jaydeep P. Kulkarni, Andres Malavasi, Charles Augustine, Carlos Tokunaga, Jim Tschanz, Muhammad M. Khellah, Vivek De
2019	—	`conf`	An All-Digital, VMAX-Compliant, and Stable Distributed Charge Injection Scheme for Fast Mitigation of Voltage Droop. ESSCIRC Suyoung Bang, Minki Cho, Pascal Meinerzhagen, Andres Malavasi, Muhammad M. Khellah, James W. Tschanz, Vivek De
2019	J	`jnl`	An Energy-Efficient Graphics Processor in 14-nm Tri-Gate CMOS Featuring Integrated Voltage Regulators for Fine-Grain DVFS, Retentive Sleep, and ${V}_{\text{MIN}}$ Optimization. IEEE J. Solid State Circuits Pascal Andreas Meinerzhagen, Carlos Tokunaga, Andres Malavasi, Vaibhav A. Vaidya, Ashwin Mendon, Deepak Mathaikutty, Jaydeep P. Kulkarni, Charles Augustine, Minki Cho, Stephen T. Kim, George E. Matthew, Rinkle Jain, Joseph F. Ryan, Chung-Ching Peng, Somnath Paul, Sriram R. Vangal, Brando Perez Esparza, Luis Cuellar, Michael Woodman, Bala Iyer, Subramaniam Maiyuran, Gautham N. Chinya, Xiang Zou, Yuyun Liao, Krishnan Ravichandran, Hong Wang, Muhammad M. Khellah, James W. Tschanz, Vivek De
2019	—	`conf`	Min-Delay Margin/Error Detection and Correction for Flip-Flops and Pulsed Latches in 10-nm CMOS. ESSCIRC Pascal Andreas Meinerzhagen, Sandip Kundu, Andres Malavasi, Trang Nguyen, Muhammad M. Khellah, James W. Tschanz, Vivek De
2018	—	`conf`	An energy-efficient graphics processor featuring fine-grain DVFS with integrated voltage regulators, execution-unit turbo, and retentive sleep in 14nm tri-gate CMOS. ISSCC Pascal Meinerzhagen, Carlos Tokunaga, Andres Malavasi, Vaibhav A. Vaidya, Ashwin Mendon, Deepak Mathaikutty, Jaydeep P. Kulkarni, Charles Augustine, Minki Cho, Stephen T. Kim, George E. Matthew, Rinkle Jain, Joseph F. Ryan, Chung-Ching Peng, Somnath Paul, Sriram R. Vangal, Brando Perez Esparza, Luis Cuellar, Michael Woodman, Bala Iyer, Subramaniam Maiyuran, Gautham N. Chinya, Chris Zou, Yuyun Liao, Krishnan Ravichandran, Hong Wang, Muhammad M. Khellah, James W. Tschanz, Vivek De
2018	J	`jnl`	Introduction to the January Special Issue on the 2017 IEEE International Solid-State Circuits Conference. IEEE J. Solid State Circuits Keith A. Bowman, Muhammad M. Khellah, Takashi Kono, Joseph Shor, Pui-In Mak
2018	—	`conf`	Session 2 overview: Processors: Digital architectures and systems subcommittee. ISSCC Thomas Burd, Muhammad M. Khellah, Byeong-Gyu Nam
2017	J	`jnl`	Postsilicon Voltage Guard-Band Reduction in a 22 nm Graphics Execution Core Using Adaptive Voltage Scaling and Dynamic Power Gating. IEEE J. Solid State Circuits Minki Cho, Stephen T. Kim, Carlos Tokunaga, Charles Augustine, Jaydeep P. Kulkarni, Krishnan Ravichandran, James W. Tschanz, Muhammad M. Khellah, Vivek De
2017	—	`conf`	Session 5 - Memory for emerging applications. CICC Muhammad M. Khellah, Rajiv V. Joshi
2016	—	`conf`	8.4 Post-silicon voltage-guard-band reduction in a 22nm graphics execution core using adaptive voltage scaling and dynamic power gating. ISSCC Minki Cho, Stephen T. Kim, Carlos Tokunaga, Charles Augustine, Jaydeep P. Kulkarni, Krishnan Ravichandran, James W. Tschanz, Muhammad M. Khellah, Vivek De
2016	—	`conf`	Adaptive clocking with dynamic power gating for mitigating energy efficiency & performance impacts of fast voltage droop in a 22nm graphics execution core. VLSI Circuits Minki Cho, Carlos Tokunaga, Stephen T. Kim, James W. Tschanz, Muhammad M. Khellah, Vivek De
2016	J	`jnl`	Enabling Wide Autonomous DVFS in a 22 nm Graphics Execution Core Using a Digitally Controlled Fully Integrated Voltage Regulator. IEEE J. Solid State Circuits Stephen T. Kim, Yi-Chun Shih, Kaushik Mazumdar, Rinkle Jain, Joseph F. Ryan, Carlos Tokunaga, Charles Augustine, Jaydeep P. Kulkarni, Krishnan Ravichandran, James W. Tschanz, Muhammad M. Khellah, Vivek De
2016	J	`jnl`	Recap of the 2016 IEEE/ACM International Symposium on Low Power Electronics and Design (ISLPED 2016). IEEE Des. Test Vijay Raghunathan, Muhammad M. Khellah
2016	C	`conf`	Synaptic sampling in hardware spiking neural networks. ISCAS Sadique Sheik, Somnath Paul, Charles Augustine, Chinnikrishna Kothapalli, Muhammad M. Khellah, Gert Cauwenberghs, Emre Neftci
2015	—	`conf`	8.6 Enabling wide autonomous DVFS in a 22nm graphics execution core using a digitally controlled hybrid LDO/switched-capacitor VR with fast droop mitigation. ISSCC Stephen T. Kim, Yi-Chun Shih, Kaushik Mazumdar, Rinkle Jain, Joseph F. Ryan, Carlos Tokunaga, Charles Augustine, Jaydeep P. Kulkarni, Krishnan Ravichandran, James W. Tschanz, Muhammad M. Khellah, Vivek De
2015	—	`conf`	A fully integrated charge sharing active decap scheme for power supply noise suppression. SoCC Ahmed M. Ammar, Rafik Guindi, Ethan Shih, Carlos Tokunaga, Jim Tschanz, Muhammad M. Khellah
2015	—	`conf`	Aging-aware Adaptive Voltage Scaling in 22nm high-K/metal-gate tri-gate CMOS. CICC Minki Cho, Carlos Tokunaga, Muhammad M. Khellah, James W. Tschanz, Vivek De
2015	—	`conf`	Designing low-VTh STT-RAM for write energy reduction in scaled technologies. ISQED Farah B. Yahya, Mohammad M. Mansour, James W. Tschanz, Muhammad M. Khellah
2014	—	`conf`	5.7 A graphics execution core in 22nm CMOS featuring adaptive clocking, selective boosting and state-retentive sleep. ISSCC Carlos Tokunaga, Joseph F. Ryan, Charles Augustine, Jaydeep P. Kulkarni, Yi-Chun Shih, Stephen T. Kim, Rinkle Jain, Keith A. Bowman, Arijit Raychowdhury, Muhammad M. Khellah, James W. Tschanz, Vivek De
2014	J	`jnl`	A 0.45-1 V Fully-Integrated Distributed Switched Capacitor DC-DC Converter With High Density MIM Capacitor in 22 nm Tri-Gate CMOS. IEEE J. Solid State Circuits Rinkle Jain, Bibiche M. Geuskens, Stephen T. Kim, Muhammad M. Khellah, Jaydeep P. Kulkarni, James W. Tschanz, Vivek De
2014	A	`ed.`	International Symposium on Low Power Electronics and Design, ISLPED'14, La Jolla, CA, USA - August 11 - 13, 2014 ISLPED Yuan Xie, Tanay Karnik, Muhammad M. Khellah, Renu Mehra
2012	—	`conf`	Capacitive-coupling wordline boosting with self-induced VCC collapse for write VMIN reduction in 22-nm 8T SRAM. ISSCC Jaydeep P. Kulkarni, Bibiche M. Geuskens, Tanay Karnik, Muhammad M. Khellah, James W. Tschanz, Vivek De
2012	—	`conf`	Characterization of Inverse Temperature Dependence in logic circuits. CICC Minki Cho, Muhammad M. Khellah, Kwanyeob Chae, Khondker Zakir Ahmed, James W. Tschanz, Saibal Mukhopadhyay
2012	A	`conf`	Design for test and reliability in ultimate CMOS. DATE Michael Nicolaidis, Lorena Anghel, Nacer-Eddine Zergainoh, Yervant Zorian, Tanay Karnik, Keith A. Bowman, James W. Tschanz, Shih-Lien Lu, Carlos Tokunaga, Arijit Raychowdhury, Muhammad M. Khellah, Jaydeep P. Kulkarni, Vivek De, Dimiter Avresky
2011	J	`jnl`	A 45 nm Resilient Microprocessor Core for Dynamic Variation Tolerance. IEEE J. Solid State Circuits Keith A. Bowman, James W. Tschanz, Shih-Lien Lu, Paolo A. Aseron, Muhammad M. Khellah, Arijit Raychowdhury, Bibiche M. Geuskens, Carlos Tokunaga, Chris Wilkerson, Tanay Karnik, Vivek K. De
2011	J	`jnl`	All-Digital Circuit-Level Dynamic Variation Monitor for Silicon Debug and Adaptive Clock Control. IEEE Trans. Circuits Syst. I Regul. Pap. Keith A. Bowman, Carlos Tokunaga, James W. Tschanz, Arijit Raychowdhury, Muhammad M. Khellah, Bibiche M. Geuskens, Shih-Lien Lu, Paolo A. Aseron, Tanay Karnik, Vivek K. De
2011	J	`jnl`	Error Detection and Correction in Microprocessor Core and Memory Due to Fast Dynamic Voltage Droops. IEEE J. Emerg. Sel. Topics Circuits Syst. Arijit Raychowdhury, Jim Tschanz, Keith A. Bowman, Shih-Lien Lu, Paolo A. Aseron, Muhammad M. Khellah, Bibiche M. Geuskens, Carlos Tokunaga, Chris Wilkerson, Tanay Karnik, Vivek De
2011	J	`jnl`	Tunable Replica Bits for Dynamic Variation Tolerance in 8T SRAM Arrays. IEEE J. Solid State Circuits Arijit Raychowdhury, Bibiche M. Geuskens, Keith A. Bowman, James W. Tschanz, Shih-Lien Lu, Tanay Karnik, Muhammad M. Khellah, Vivek K. De
2010	—	`conf`	A 45nm resilient and adaptive microprocessor core for dynamic variation tolerance. ISSCC James W. Tschanz, Keith A. Bowman, Shih-Lien Lu, Paolo A. Aseron, Muhammad M. Khellah, Arijit Raychowdhury, Bibiche M. Geuskens, Carlos Tokunaga, Chris Wilkerson, Tanay Karnik, Vivek De
2010	—	`conf`	Dynamic variation monitor for measuring the impact of voltage droops on microprocessor clock frequency. CICC Keith A. Bowman, Carlos Tokunaga, James W. Tschanz, Arijit Raychowdhury, Muhammad M. Khellah, Bibiche M. Geuskens, Shih-Lien Lu, Paolo A. Aseron, Tanay Karnik, Vivek De
2010	J	`jnl`	Multi-Phase 1 GHz Voltage Doubler Charge Pump in 32 nm Logic Process. IEEE J. Solid State Circuits Dinesh Somasekhar, Balaji Srinivasan, Gunjan Pandya, Fatih Hamzaoglu, Muhammad M. Khellah, Tanay Karnik, Kevin Zhang
2010	—	`conf`	Opportunities for PMOS read and write ports in low voltage dual-port 8T bit cell arrays. CICC Bibiche M. Geuskens, Muhammad M. Khellah, Jaydeep P. Kulkarni, Tanay Karnik, Vivek De
2010	—	`conf`	PVT-and-aging adaptive wordline boosting for 8T SRAM power reduction. ISSCC Arijit Raychowdhury, Bibiche M. Geuskens, Jaydeep P. Kulkarni, James W. Tschanz, Keith A. Bowman, Tanay Karnik, Shih-Lien Lu, Vivek De, Muhammad M. Khellah
2010	—	`conf`	Resilient design in scaled CMOS for energy efficiency. ASP-DAC James W. Tschanz, Keith A. Bowman, Muhammad M. Khellah, Chris Wilkerson, Bibiche M. Geuskens, Dinesh Somasekhar, Arijit Raychowdhury, Jaydeep P. Kulkarni, Carlos Tokunaga, Shih-Lien Lu, Tanay Karnik, Vivek De
2010	A	`conf`	Resilient microprocessor design for high performance & energy efficiency. ISLPED Keith A. Bowman, James W. Tschanz, Shih-Lien Lu, Paolo A. Aseron, Muhammad M. Khellah, Arijit Raychowdhury, Bibiche M. Geuskens, Carlos Tokunaga, Chris Wilkerson, Tanay Karnik, Vivek De
2009	J	`jnl`	2 GHz 2 Mb 2T Gain Cell Memory Macro With 128 GBytes/sec Bandwidth in a 65 nm Logic Process Technology. IEEE J. Solid State Circuits Dinesh Somasekhar, Yibin Ye, Paolo A. Aseron, Shih-Lien Lu, Muhammad M. Khellah, Jason Howard, Gregory Ruhl, Tanay Karnik, Shekhar Borkar, Vivek K. De, Ali Keshavarzi
2009	J	`jnl`	Process, Temperature, and Supply-Noise Tolerant 45nm Dense Cache Arrays With Diffusion-Notch-Free (DNF) 6T SRAM Cells and Dynamic Multi-Vcc Circuits. IEEE J. Solid State Circuits Muhammad M. Khellah, Nam-Sung Kim, Yibin Ye, Dinesh Somasekhar, Tanay Karnik, Nitin Borkar, Gunjan Pandya, Fatih Hamzaoglu, Tom Coan, Yih Wang, Kevin Zhang, Clair Webb, Vivek De
2009	J	`jnl`	SRAM dynamic stability estimation using MPFP and its applications. Microelectron. J. DiaaEldin Khalil, Muhammad M. Khellah, Nam-Sung Kim, Yehea I. Ismail, Tanay Karnik, Vivek De
2009	J	`jnl`	SSMCB: Low-Power Variation-Tolerant Source-Synchronous Multicycle Bus. IEEE Trans. Circuits Syst. I Regul. Pap. Maged Ghoneima, Yehea I. Ismail, Muhammad M. Khellah, Vivek De
2009	J	`jnl`	Serial-Link Bus: A Low-Power On-Chip Bus Architecture. IEEE Trans. Circuits Syst. I Regul. Pap. Maged Ghoneima, Yehea I. Ismail, Muhammad M. Khellah, James W. Tschanz, Vivek De
2009	J	`jnl`	Trading Off Cache Capacity for Low-Voltage Operation. IEEE Micro Chris Wilkerson, Hongliang Gao, Alaa R. Alameldeen, Zeshan Chishti, Muhammad M. Khellah, Shih-Lien Lu
2008	—	`conf`	2GHz 2Mb 2T Gain-Cell Memory Macro with 128GB/s Bandwidth in a 65nm Logic Process. ISSCC Dinesh Somasekhar, Yibin Ye, Paolo A. Aseron, Shih-Lien Lu, Muhammad M. Khellah, Jason Howard, Gregory Ruhl, Tanay Karnik, Shekhar Y. Borkar, Vivek De, Ali Keshavarzi
2008	J	`jnl`	Accurate Estimation of SRAM Dynamic Stability. IEEE Trans. Very Large Scale Integr. Syst. D. E. Khalil, Muhammad M. Khellah, Nam-Sung Kim, Yehea I. Ismail, Tanay Karnik, Vivek K. De
2008	—	`conf`	Analytical Model for the Propagation Delay of Through Silicon Vias. ISQED DiaaEldin Khalil, Yehea I. Ismail, Muhammad M. Khellah, Tanay Karnik, Vivek De
2008	J	`jnl`	Skewed Repeater Bus: A Low-Power Scheme for On-Chip Buses. IEEE Trans. Circuits Syst. I Regul. Pap. Maged Ghoneima, Muhammad M. Khellah, James W. Tschanz, Yibin Ye, Nasser A. Kurd, Javed Barkatullah, Srikanth Nimmagadda, Yehea I. Ismail, Vivek K. De
2008	A*	`conf`	Trading off Cache Capacity for Reliability to Enable Low Voltage Operation. ISCA Chris Wilkerson, Hongliang Gao, Alaa R. Alameldeen, Zeshan Chishti, Muhammad M. Khellah, Shih-Lien Lu
2007	J	`jnl`	A 256-Kb Dual-V IEEE J. Solid State Circuits Muhammad M. Khellah, Dinesh Somasekhar, Yibin Ye, Nam-Sung Kim, Jason Howard, Gregory Ruhl, Murad Sunna, James W. Tschanz, Nitin Borkar, Fatih Hamzaoglu, Gunjan Pandya, Ali Farhang, Kevin Zhang, Vivek De
2007	J	`jnl`	Variation-Tolerant and Low-Power Source-Synchronous Multicycle On-Chip Interconnect Scheme. VLSI Design Maged Ghoneima, Yehea I. Ismail, Muhammad M. Khellah, Vivek De
2007	J	`jnl`	Variations-Aware Low-Power Design and Block Clustering With Voltage Scaling. IEEE Trans. Very Large Scale Integr. Syst. Navid Azizi, Muhammad M. Khellah, Vivek De, Farid N. Najm
2006	—	`conf`	A 4.2GHz 0.3mm2 256kb Dual-V ISSCC Muhammad M. Khellah, Nam-Sung Kim, Jason Howard, Gregory Ruhl, Yibin Ye, James W. Tschanz, Dinesh Somasekhar, Nitin Borkar, Fatih Hamzaoglu, Gunjan Pandya, Ali Farhang, Kevin Zhang, Vivek De
2006	C	`conf`	Evaluation of differential vs. single-ended sensing and asymmetric cells in 90 nm logic technology for on-chip caches. ISCAS Yibin Ye, Muhammad M. Khellah, Dinesh Somasekhar, Vivek De
2006	J	`jnl`	Formal derivation of optimal active shielding for low-power on-chip buses. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. Maged Ghoneima, Yehea I. Ismail, Muhammad M. Khellah, James W. Tschanz, Vivek De
2006	—	`conf`	Reducing the Data Switching Activity on Serial Link Buses. ISQED Maged Ghoneima, Yehea I. Ismail, Muhammad M. Khellah, Vivek De
2006	J	`jnl`	Reducing the Effective Coupling Capacitance in Buses Using Threshold Voltage Adjustment Techniques. IEEE Trans. Circuits Syst. I Regul. Pap. Maged Ghoneima, Yehea I. Ismail, Muhammad M. Khellah, James W. Tschanz, Vivek De
2006	C	`conf`	Reducing the data switching activity of serialized datastreams. ISCAS Maged Ghoneima, Yehea I. Ismail, Muhammad M. Khellah, Vivek De
2006	A	`conf`	Time-borrowing multi-cycle on-chip interconnects for delay variation tolerance. ISLPED Keith A. Bowman, James W. Tschanz, Muhammad M. Khellah, Maged Ghoneima, Yehea I. Ismail, Vivek De
2005	C	`conf`	A Skewed Repeater Bus Architecture for On-Chip Energy Reduction in Microprocessors. ICCD Muhammad M. Khellah, Maged Ghoneima, James W. Tschanz, Yibin Ye, Nasser A. Kurd, Javed Barkatullah, Srikanth Nimmagadda, Yehea I. Ismail
2005	A	`conf`	Serial-link bus: a low-power on-chip bus architecture. ICCAD Maged Ghoneima, Yehea I. Ismail, Muhammad M. Khellah, James W. Tschanz, Vivek De
2005	—	`conf`	Skewing adjacent line repeaters to reduce the delay and energy dissipation of on-chip buses. ISCAS (1) Yehea I. Ismail, Muhammad M. Khellah, Maged Ghoneima, James W. Tschanz, Yibin Ye, Vivek De
2005	A*	`conf`	Variations-aware low-power design with voltage scaling. DAC Navid Azizi, Muhammad M. Khellah, Vivek De, Farid N. Najm
2003	J	`jnl`	A 6-GHz 16-kB L1 cache in a 100-nm dual-V IEEE J. Solid State Circuits Yibin Ye, Muhammad M. Khellah, Dinesh Somasekhar, Ali Farhang, Vivek De
2001	J	`jnl`	A low-power high-performance current-mode multiport SRAM. IEEE Trans. Very Large Scale Integr. Syst. Muhammad M. Khellah, Mohamed I. Elmasry
1998	—	`conf`	A Low-Power High-Performance Embedded SRAM Macrocell. Great Lakes Symposium on VLSI Amr M. Fahim, Muhammad M. Khellah, Mohamed I. Elmasry
1998	—	`conf`	Effective Capacitance Macro-Modelling for Architectural-Level Power Estimation. Great Lakes Symposium on VLSI Muhammad M. Khellah, Mohamed I. Elmasry
1996	J	`jnl`	Minimizing FPGA Interconnect Delays. IEEE Des. Test Comput. Stephen Brown, Muhammad M. Khellah, Zvonko G. Vranesic
1996	J	`jnl`	Segmented Routing for Speed-Performance and Routability in Field-Programmable Gate Arrays. VLSI Design Stephen Brown, Muhammad M. Khellah, Guy Lemieux