Mudit Bhargava

31 papers A* 2A 6C 2Journal 6Unranked 14

Year	Rank	Type	Title / Venue / Authors
2025	A	`conf`	Invited Paper: System and Technology Co-Optimization Framework for a Disaggregated System with Passive Die 2.5D Integration. ICCAD Gauthaman Murali, Mudit Bhargava, Shairfe Salahuddin, Zhichao Chen, Archana Pandey, Srivatsa Rangachar Srinivasa, Prerna Budhkar, Ragh Kuttappa, Vinayak Honkote, Prashanth Sakthi, Myung-Hee Na, Tanay Karnik
2023	J	`jnl`	A survey of Digital Manufacturing Hardware and Software Trojans. CoRR Prithwish Basu Roy, Mudit Bhargava, Chia-Yun Chang, Ellen Hui, Nikhil Gupta, Ramesh Karri, Hammond Pearce
2021	—	`conf`	3D-Split SRAM: Enabling Generational Gains in Advanced CMOS. CICC Rahul Mathur, Mudit Bhargava, Heath Perry, Alberto Cestero, Frank Frederick, Shawn Hung, Chien-Ju Chao, Daniel Smith, Daniel Fisher, Norman Robson, Xiaoqing Xu, Pranavi Chandupatla, Raguram Balachandran, Saurabh Sinha, Brian Cline, Jaydeep P. Kulkarni
2021	J	`jnl`	A Compact Model for Scalable MTJ Simulation. CoRR Fernando García-Redondo, Pranay Prabhat, Mudit Bhargava, Cyrille Dray
2021	—	`conf`	A Fokker-Planck Solver to Model MTJ Stochasticity. ESSDERC Fernando García-Redondo, Pranay Prabhat, Mudit Bhargava
2021	J	`jnl`	A Fokker-Planck Solver to Model MTJ Stochasticity. CoRR Fernando García-Redondo, Pranay Prabhat, Mudit Bhargava
2020	J	`jnl`	Stack up your chips: Betting on 3D integration to augment Moore's Law scaling. CoRR Saurabh Sinha, Xiaoqing Xu, Mudit Bhargava, Shidhartha Das, Brian Cline, Greg Yeric
2019	—	`conf`	A 4GHz 16nm SRAM Architecture with Low-Power Features for Heterogeneous Computing Platforms. VLSI Circuits Cagla Cakir, Andy W. Chen, Y. K. Chong, Sriram Thyagarajan, Mark P. McCartney, Peixuan Tan, Yulin Shi, Mudit Bhargava
2019	A	`conf`	Enhanced 3D Implementation of an Arm ISLPED Xiaoqing Xu, Mudit Bhargava, Steve Moore, Saurabh Sinha, Brian Cline
2019	A*	`conf`	On-Chip Memory Technology Design Space Explorations for Mobile Deep Neural Network Accelerators. DAC Haitong Li, Mudit Bhargava, Paul N. Whatmough, H.-S. Philip Wong
2019	J	`jnl`	Secure hardware-entangled field programmable gate arrays. J. Parallel Distributed Comput. Burak Erbagci, Nail Etkin Can Akkaya, Mudit Bhargava, Rachel Dondero, Ken Mai
2015	J	`jnl`	A High Reliability PUF Using Hot Carrier Injection Based Response Reinforcement. IACR Cryptol. ePrint Arch. Mudit Bhargava, Ken Mai
2015	—	`conf`	Deeply hardware-entangled reconfigurable logic and interconnect. ReConFig Burak Erbagci, Mudit Bhargava, Rachel Dondero, Ken Mai
2015	—	`conf`	Robust true random number generator using hot-carrier injection balanced metastable sense amplifiers. HOST Mudit Bhargava, Kaship Sheikh, Ken Mai
2014	A	`conf`	An efficient reliable PUF-based cryptographic key generator in 65nm CMOS. DATE Mudit Bhargava, Ken Mai
2014	—	`conf`	Low VMIN 20nm embedded SRAM with multi-voltage wordline control based read and write assist techniques. VLSIC Mudit Bhargava, Y. K. Chong, Vincent Schuppe, Bikas Maiti, Martin Kinkade, Hsin-Yu Chen, Andy W. Chen, Sanjay Mangal, Jacek Wiatrowski, Gerald Gouya, Abhishek Baradia, Sriram Thyagarajan, Gus Yeung
2013	A	`conf`	A High Reliability PUF Using Hot Carrier Injection Based Response Reinforcement. CHES Mudit Bhargava, Ken Mai
2013	C	`conf`	Building Fast, Dense, Low-Power Caches Using Erasure-Based Inline Multi-bit ECC. PRDC Jangwoo Kim, Hyunggyun Yang, Mark P. McCartney, Mudit Bhargava, Ken Mai, Babak Falsafi
2013	—	`—`	Reliable, Secure, Efficient Physical Unclonable Functions. Mudit Bhargava
2013	A	`conf`	SCAN-PUF: A low overhead Physically Unclonable Function from scan chain power-up states. ITC Ben Niewenhuis, Ronald D. Blanton, Mudit Bhargava, Ken Mai
2013	—	`conf`	Stylometric Analysis for Authorship Attribution on Twitter. BDA Mudit Bhargava, Pulkit Mehndiratta, Krishna Asawa
2012	—	`conf`	6T SRAM and 3T DRAM data retention and remanence characterization in 65nm bulk CMOS. CICC Cagla Cakir, Mudit Bhargava, Ken Mai
2012	—	`conf`	Comparison of bi-stable and delay-based Physical Unclonable Functions from measurements in 65nm bulk CMOS. CICC Mudit Bhargava, Cagla Cakir, Ken Mai
2012	—	`conf`	Reliability enhancement of bi-stable PUFs in 65nm bulk CMOS. HOST Mudit Bhargava, Cagla Cakir, Ken Mai
2011	A	`conf`	FPGA-based nand flash memory error characterization and solid-state drive prototyping platform (abstract only). FPGA Yu Cai, Erich F. Haratsch, Mark P. McCartney, Mudit Bhargava, Ken Mai
2010	—	`conf`	Attack Resistant Sense Amplifier based PUFs (SA-PUF) with Deterministic and Controllable Reliability of PUF Responses. HOST Mudit Bhargava, Cagla Cakir, Ken Mai
2010	—	`conf`	Side-channel Attack Resistant ROM-based AES S-Box. HOST Craig Teegarden, Mudit Bhargava, Ken Mai
2010	A*	`conf`	Virtual prototyper (ViPro): an early design space exploration and optimization tool for SRAM designers. DAC Satyanand Nalam, Mudit Bhargava, Ken Mai, Benton H. Calhoun
2009	C	`conf`	A Technology-Agnostic Simulation Environment (TASE) for iterative custom IC design across processes. ICCD Satyanand Nalam, Mudit Bhargava, Kyle Ringgenberg, Ken Mai, Benton H. Calhoun
2009	—	`conf`	Low-overhead, digital offset compensated, SRAM sense amplifiers. CICC Mudit Bhargava, Mark P. McCartney, Alexander Hoefler, Ken Mai
2008	—	`conf`	Variation-tolerant SRAM sense-amplifier timing using configurable replica bitlines. CICC Umut Arslan, Mark P. McCartney, Mudit Bhargava, Xin Li, Ken Mai, Lawrence T. Pileggi