Mubin Ul Haque

15 papers A 3B 1C 1Misc 1Journal 8Unranked 1
YearRankTypeTitle / Venue / Authors
2024 J jnl
Detection of Animal Movement from Weather Radar using Self-Supervised Learning.
CoRR
Mubin Ul Haque, Joel Janek Dabrowski, Rebecca M. Rogers, Hazel Parry
2023 B conf
A Study on Early & Non-Intrusive Security Assessment for Container Images.
ENASE
Mubin Ul Haque, Muhammad Ali Babar
2022 J jnl
"I think this is the most disruptive technology": Exploring Sentiments of ChatGPT Early Adopters using Twitter Data.
CoRR
Mubin Ul Haque, Isuru Dharmadasa, Zarrin Tasnim Sworna, Roshan Namal Rajapakse, Hussain Ahmad
2022 J jnl
A Cost-Efficient Look-Up Table Based Binary Coded Decimal Adder Design.
CoRR
Zarrin Tasnim Sworna, Mubin Ul Haque, Hafiz Md. Hasan Babu, Lafifa Jamal
2022 A conf
KGSecConfig: A Knowledge Graph Based Approach for Secured Container Orchestrator Configuration.
SANER
Mubin Ul Haque, M. Mehdi Kholoosi, Muhammad Ali Babar
2022 A conf
Well Begun is Half Done: An Empirical Study of Exploitability & Impact of Base-Image Vulnerabilities.
SANER
Mubin Ul Haque, Muhammad Ali Babar
2021 J jnl
KGSecConfig: A Knowledge Graph Based Approach for Secured Container Orchestrator Configuration.
CoRR
Mubin Ul Haque, M. Mehdi Kholoosi, Muhammad Ali Babar
2021 J jnl
Well Begun is Half Done: An Empirical Study of Exploitability & Impact of Base-Image Vulnerabilities.
CoRR
Mubin Ul Haque, Muhammad Ali Babar
2020 A conf
Challenges in Docker Development: A Large-scale Study Using Stack Overflow.
ESEM
Mubin Ul Haque, Leonardo Horn Iwaya, Muhammad Ali Babar
2020 J jnl
Challenges in Docker Development: A Large-scale Study Using Stack Overflow.
CoRR
Mubin Ul Haque, Leonardo Horn Iwaya, Muhammad Ali Babar
2018 J jnl
A Fast FPGA-Based BCD Adder.
Circuits Syst. Signal Process.
Mubin Ul Haque, Zarrin Tasnim Sworna, Hafiz Md. Hasan Babu, Ashis Kumer Biswas
2017 — conf
An Efficient Design of an FPGA-Based Multiplier Using LUT Merging Theorem.
ISVLSI
Zarrin Tasnim Sworna, Mubin Ul Haque, Hafiz Md. Hasan Babu, Lafifa Jamal, Ashis Kumer Biswas
2016 C conf
A LUT-based matrix multiplication using neural networks.
ISCAS
Zarrin Tasnim Sworna, Mubin Ul Haque, Hafiz Md. Hasan Babu
2016 Misc conf
An Improved Design of a Reversible Fault Tolerant LUT-based FPGA.
VLSID
Mubin Ul Haque, Zarrin Tasnim Sworna, Hafiz Md. Hasan Babu
2016 J jnl
Low-power and area efficient binary coded decimal adder design using a look up table-based field programmable gate array.
IET Circuits Devices Syst.
Zarrin Tasnim Sworna, Mubin Ul Haque, Nazma Tara, Hafiz Md. Hasan Babu, Ashis Kumer Biswas