Mu-Tien Chang

12 papers A* 1B 2Journal 1Unranked 7
YearRankTypeTitle / Venue / Authors
2018 — conf
Performance Impact of Emerging Memory Technologies on Big Data Applications: A Latency-Programmable System Emulation Approach.
ACM Great Lakes Symposium on VLSI
Mu-Tien Chang, I. Stephen Choi, Dimin Niu, Hongzhong Zheng
2017 — conf
Architecting HBM as a high bandwidth, high capacity, self-managed last-level cache.
PDSW-DISCS@SC
Tyler Stocksdale, Mu-Tien Chang, Hongzhong Zheng, Frank Mueller
2017 — conf
FlashStorageSim: Performance Modeling for SSD Architectures.
NAS
Krishna T. Malladi, Mu-Tien Chang, Dimin Niu, Hongzhong Zheng
2016 J jnl
DRAM Refresh Mechanisms, Penalties, and Trade-Offs.
IEEE Trans. Computers
Ishwar Bhati, Mu-Tien Chang, Zeshan Chishti, Shih-Lien Lu, Bruce L. Jacob
2015 B conf
FAME: A Fast and Accurate Memory Emulator for New Memory System Architecture Exploration.
MASCOTS
Krishna T. Malladi, Mu-Tien Chang, John Ping, Hongzhong Zheng
2013 — —
Technology Implications for Large Last-Level Caches.
Mu-Tien Chang
2013 A* conf
Technology comparison for large last-level caches (L
HPCA
Mu-Tien Chang, Paul Rosenfeld, Shih-Lien Lu, Bruce L. Jacob
2012 B conf
Energy-Efficient Cached DIMM Architecture.
MASCOTS
Mu-Tien Chang, Joe Gross, Bruce L. Jacob
2011 — conf
An analytical model to estimate PCM failure probability due to process variations.
SoCC
Mu-Tien Chang, Bruce L. Jacob
2008 — conf
A fully-differential subthreshold SRAM cell with auto-compensation.
APCCAS
Mu-Tien Chang, Wei Hwang
2008 — conf
A robust ultra-low power asynchronous FIFO memory with self-adaptive power control.
SoCC
Mu-Tien Chang, Po-Tsang Huang, Wei Hwang
2007 — conf
A 65nm low power 2T1D embedded DRAM with leakage current reduction.
SoCC
Mu-Tien Chang, Po-Tsang Huang, Wei Hwang