Mrunmay Talegaonkar

30 papers Journal 15Unranked 15
YearRankTypeTitle / Venue / Authors
2018 J jnl
A 0.45-0.7 V 1-6 Gb/s 0.29-0.58 pJ/b Source-Synchronous Transceiver Using Near-Threshold Operation.
IEEE J. Solid State Circuits
Woo-Seok Choi, Guanghua Shu, Mrunmay Talegaonkar, Yubo Liu, Da Wei, Luca Benini, Pavan Kumar Hanumolu
2018 J jnl
A 12-Gb/s -16.8-dBm OMA Sensitivity 23-mW Optical Receiver in 65-nm CMOS.
IEEE J. Solid State Circuits
Mostafa Gamal Ahmed, Mrunmay Talegaonkar, Ahmed Elkholy, Guanghua Shu, Ahmed Elmallah, Alexander V. Rylyakov, Pavan Kumar Hanumolu
2017 — conf
29.6 A 3-to-10Gb/s 5.75pJ/b transceiver with flexible clocking in 65nm CMOS.
ISSCC
Romesh Kumar Nandwana, Saurabh Saxena, Ahmed Elkholy, Mrunmay Talegaonkar, Junheng Zhu, Woo-Seok Choi, Ahmed Elmallah, Pavan Kumar Hanumolu
2017 — conf
A 0.7V time-based inductor for fully integrated low bandwidth filter applications.
CICC
Braedon Salz, Mrunmay Talegaonkar, Guanghua Shu, Ahmed Elmallah, Romesh Kumar Nandwana, Bibhudatta Sahoo, Pavan Kumar Hanumolu
2017 J jnl
A 2.8 mW/Gb/s, 14 Gb/s Serial Link Transceiver.
IEEE J. Solid State Circuits
Saurabh Saxena, Guanghua Shu, Romesh Kumar Nandwana, Mrunmay Talegaonkar, Ahmed Elkholy, Tejasvi Anand, Woo-Seok Choi, Pavan Kumar Hanumolu
2017 J jnl
A 5GHz Digital Fractional-N PLL Using a 1-bit Delta-Sigma Frequency-to-Digital Converter in 65 nm CMOS.
IEEE J. Solid State Circuits
Mrunmay Talegaonkar, Tejasvi Anand, Ahmed Elkholy, Amr Elshazly, Romesh Kumar Nandwana, Saurabh Saxena, Brian Young, Woo-Seok Choi, Pavan Kumar Hanumolu
2016 — conf
23.1 A 16Mb/s-to-8Gb/s 14.1-to-5.9pJ/b source synchronous transceiver using DVFS and rapid on/off in 65nm CMOS.
ISSCC
Guanghua Shu, Woo-Seok Choi, Saurabh Saxena, Seong Joong Kim, Mrunmay Talegaonkar, Romesh Kumar Nandwana, Ahmed Elkholy, Da Wei, Timir Nandi, Pavan Kumar Hanumolu
2016 J jnl
A 4-to-10.5 Gb/s Continuous-Rate Digital Clock and Data Recovery With Automatic Frequency Acquisition.
IEEE J. Solid State Circuits
Guanghua Shu, Woo-Seok Choi, Saurabh Saxena, Mrunmay Talegaonkar, Tejasvi Anand, Ahmed Elkholy, Amr Elshazly, Pavan Kumar Hanumolu
2015 — conf
10.7 A 6.75-to-8.25GHz 2.25mW 190fsrms integrated-jitter PVT-insensitive injection-locked clock multiplier using all-digital continuous frequency-tracking loop in 65nm CMOS.
ISSCC
Ahmed Elkholy, Mrunmay Talegaonkar, Tejasvi Anand, Pavan Kumar Hanumolu
2015 — conf
3.7 A 7Gb/s rapid on/off embedded-clock serial-link transceiver with 20ns power-on time, 740μW off-state power for energy-proportional links in 65nm CMOS.
ISSCC
Tejasvi Anand, Mrunmay Talegaonkar, Ahmed Elkholy, Saurabh Saxena, Amr Elshazly, Pavan Kumar Hanumolu
2015 — conf
3.8 A 0.45-to-0.7V 1-to-6Gb/S 0.29-to-0.58pJ/b source-synchronous transceiver using automatic phase calibration in 65nm CMOS.
ISSCC
Woo-Seok Choi, Guanghua Shu, Mrunmay Talegaonkar, Yubo Liu, Da Wei, Luca Benini, Pavan Kumar Hanumolu
2015 — conf
A 2.8mW/Gb/s 14Gb/s serial link transceiver in 65nm CMOS.
VLSIC
Saurabh Saxena, Guanghua Shu, Romesh Kumar Nandwana, Mrunmay Talegaonkar, Ahmed Elkholy, Tejasvi Anand, Seong Joong Kim, Woo-Seok Choi, Pavan Kumar Hanumolu
2015 J jnl
A 7 Gb/s Embedded Clock Transceiver for Energy Proportional Links.
IEEE J. Solid State Circuits
Tejasvi Anand, Mrunmay Talegaonkar, Ahmed Elkholy, Saurabh Saxena, Amr Elshazly, Pavan Kumar Hanumolu
2015 J jnl
A Calibration-Free Fractional-N Ring PLL Using Hybrid Phase/Current-Mode Phase Interpolation Method.
IEEE J. Solid State Circuits
Romesh Kumar Nandwana, Tejasvi Anand, Saurabh Saxena, Seong Joong Kim, Mrunmay Talegaonkar, Ahmed Elkholy, Woo-Seok Choi, Amr Elshazly, Pavan Kumar Hanumolu
2015 J jnl
Design and Analysis of Low-Power High-Frequency Robust Sub-Harmonic Injection-Locked Clock Multipliers.
IEEE J. Solid State Circuits
Ahmed Elkholy, Mrunmay Talegaonkar, Tejasvi Anand, Pavan Kumar Hanumolu
2015 J jnl
High Frequency Buck Converter Design Using Time-Based Control Techniques.
IEEE J. Solid State Circuits
Seong Joong Kim, Qadeer Khan, Mrunmay Talegaonkar, Amr Elshazly, Arun Rao, Nathanael Griesert, Greg Winter, William McIntyre, Pavan Kumar Hanumolu
2014 — conf
A 10-25MHz, 600mA buck converter using time-based PID compensator with 2µA/MHz quiescent current, 94% peak efficiency, and 1MHz BW.
VLSIC
Qadeer Ahmad Khan, Seong Joong Kim, Mrunmay Talegaonkar, Amr Elshazly, Arun Rao, Nathanael Griesert, Greg Winter, William McIntyre, Pavan Kumar Hanumolu
2014 — conf
A 4.25GHz-4.75GHz calibration-free fractional-N ring PLL using hybrid phase/current-mode phase interpolator with 13.2dB phase noise improvement.
VLSIC
Romesh Kumar Nandwana, Tejasvi Anand, Saurabh Saxena, Seong Joong Kim, Mrunmay Talegaonkar, Ahmed Elkholy, Woo-Seok Choi, Amr Elshazly, Pavan Kumar Hanumolu
2014 — conf
A 4.4-5.4GHz digital fractional-N PLL using ΔΣ frequency-to-digital converter.
VLSIC
Mrunmay Talegaonkar, Tejasvi Anand, Ahmed Elkholy, Amr Elshazly, Romesh Kumar Nandwana, Saurabh Saxena, Brian Young, Woo-Seok Choi, Pavan Kumar Hanumolu
2014 J jnl
A 5 Gb/s, 10 ns Power-On-Time, 36 µW Off-State Power, Fast Power-On Transmitter for Energy Proportional Links.
IEEE J. Solid State Circuits
Tejasvi Anand, Amr Elshazly, Mrunmay Talegaonkar, Brian Young, Pavan Kumar Hanumolu
2014 J jnl
A Reference-Less Clock and Data Recovery Circuit Using Phase-Rotating Phase-Locked Loop.
IEEE J. Solid State Circuits
Guanghua Shu, Saurabh Saxena, Woo-Seok Choi, Mrunmay Talegaonkar, Rajesh Inti, Amr Elshazly, Brian Young, Pavan Kumar Hanumolu
2014 J jnl
An 8 Gb/s-64 Mb/s, 2.3-4.2 mW/Gb/s Burst-Mode Transmitter in 90 nm CMOS.
IEEE J. Solid State Circuits
Mrunmay Talegaonkar, Amr Elshazly, Karthikeyan Reddy, Praveen Prabha, Tejasvi Anand, Pavan Kumar Hanumolu
2013 — conf
A 2.5GHz 2.2mW/25µW on/off-state power 2psrms-long-term-jitter digital clock multiplier with 3-reference-cycles power-on time.
ISSCC
Tejasvi Anand, Mrunmay Talegaonkar, Amr Elshazly, Brian Young, Pavan Kumar Hanumolu
2012 — conf
A 0.55V 61dB-SNR 67dB-SFDR 7MHz 4
ISSCC
Brian Drost, Mrunmay Talegaonkar, Pavan Kumar Hanumolu
2012 — conf
A 1.5GHz 1.35mW -112dBc/Hz in-band noise digital phase-locked loop with 50fs/mV supply-noise sensitivity.
VLSIC
Amr Elshazly, Rajesh Inti, Mrunmay Talegaonkar, Pavan Kumar Hanumolu
2012 J jnl
A 16-mW 78-dB SNDR 10-MHz BW CT Delta Sigma ADC Using Residue-Cancelling VCO-Based Quantizer.
IEEE J. Solid State Circuits
Karthikeyan Reddy, Sachin Rao, Rajesh Inti, Brian Young, Amr Elshazly, Mrunmay Talegaonkar, Pavan Kumar Hanumolu
2012 — conf
A 16mW 78dB-SNDR 10MHz-BW CT-ΔΣ ADC using residue-cancelling VCO-based quantizer.
ISSCC
Karthikeyan Reddy, Sachin Rao, Rajesh Inti, Brian Young, Amr Elshazly, Mrunmay Talegaonkar, Pavan Kumar Hanumolu
2012 J jnl
Analog Filter Design Using Ring Oscillator Integrators.
IEEE J. Solid State Circuits
Brian Drost, Mrunmay Talegaonkar, Pavan Kumar Hanumolu
2011 J jnl
A TDC-Less 7 mW 2.5 Gb/s Digital CDR With Linear Loop Dynamics and Offset-Free Data Recovery.
IEEE J. Solid State Circuits
Wenjing Yin, Rajesh Inti, Amr Elshazly, Mrunmay Talegaonkar, Brian Young, Pavan Kumar Hanumolu
2011 — conf
Digital clock and data recovery circuit design: Challenges and tradeoffs.
CICC
Mrunmay Talegaonkar, Rajesh Inti, Pavan Kumar Hanumolu