Mototsugu Hamada

90 papers A* 1B 1C 8Journal 33Unranked 47

Year	Rank	Type	Title / Venue / Authors
2026	J	`jnl`	A Connectivity-Aware Via-Programmable DNN Processor Using a Single Photomask. IEEE Open J. Circuits Syst. Jaewon Shin, Mototsugu Hamada, Atsutake Kosuge
2026	—	`conf`	Analysis and Design of Oblong Coils and Standard-Cell-Based Receiver for Area-Efficient Edge-Coupled Inductive Coupling Transceiver. ASP-DAC Yuki Mitarai, Mototsugu Hamada, Atsutake Kosuge
2025	—	`conf`	13.6 A Via-Programmable DNN-Processor Fabrication Toward 1/40 ISSCC Jaewon Shin, Rei Sumikawa, Dongzhu Li, Mototsugu Hamada, Atsutake Kosuge
2025	C	`conf`	A 83.7% Resource Reduced FPGA-based Wired-Logic DNN Processor by Using Mixed-Precision Module Embedding Into Non-Linear Function LUT. ISCAS Yuxuan Pan, Mototsugu Hamada, Atsutake Kosuge
2025	—	`conf`	A Coarse- and Fine-Grained LUT Segmentation Method Enabling Single FPGA Implementation of Wired-Logic DNN Processor. ASP-DAC Yuxuan Pan, Dongzhu Li, Mototsugu Hamada, Atsutake Kosuge
2025	J	`jnl`	Analysis and Design of Coarse and Fine Segmented LUT Implementation for FPGA-Based Resource Efficient Wired-Logic DNN Processors. IEICE Trans. Electron. Yuxuan Pan, Dongzhu Li, Mototsugu Hamada, Atsutake Kosuge
2024	J	`jnl`	A 0.13mJ/Prediction CIFAR-100 Fully Synthesizable Raster-Scan-Based Wired-Logic Processor in 16-nm FPGA. IEICE Trans. Electron. Dongzhu Li, Zhijie Zhan, Rei Sumikawa, Mototsugu Hamada, Atsutake Kosuge, Tadahiro Kuroda
2024	—	`conf`	A 250.3μW Versatile Sound Feature Extractor Using 1024-point FFT 64-ch LogMel Filter in 40nm CMOS. APCCAS Akiho Kawada, Kenji Kobayashi, Jaewon Shin, Rei Sumikawa, Mototsugu Hamada, Atsutake Kosuge
2024	C	`conf`	Efficient FPGA Resource Utilization in Wired-Logic Processors Using Coarse and Fine Segmentation of LUTs for Non-Linear Functions. ISCAS Dongzhu Li, Tianqi Zhao, Kenji Kobayashi, Atsutake Kosuge, Mototsugu Hamada, Tadahiro Kuroda
2024	J	`jnl`	Introduction to the Special Issue on the 2023 Symposium on VLSI Circuits. IEEE J. Solid State Circuits Mototsugu Hamada, Ron Kapusta
2023	C	`conf`	A 0.13mJ/Prediction CIFAR-100 Raster-Scan- Based Wired-Logic Processor Using Non-Linear Neural Network. ISCAS Dongzhu Li, Yao-Chung Hsu, Rei Sumikawa, Atsutake Kosuge, Mototsugu Hamada, Tadahiro Kuroda
2023	—	`conf`	A 1.2nJ/Classification Fully Synthesized All-Digital Asynchronous Wired-Logic Processor Using Quantized Non-Linear Function Blocks in 0.18μm CMOS. ASP-DAC Rei Sumikawa, Kota Shiba, Atsutake Kosuge, Mototsugu Hamada, Tadahiro Kuroda
2023	J	`jnl`	A 10.7-µJ/Frame 88% Accuracy CIFAR-10 Single-Chip Neuromorphic Field-Programmable Gate Array Processor Featuring Various Nonlinear Functions of Dendrites in the Human Cerebrum. IEEE Micro Atsutake Kosuge, Yao-Chung Hsu, Rei Sumikawa, Mototsugu Hamada, Tadahiro Kuroda, Tomoe Ishikawa
2023	—	`conf`	A 183.4nJ/inference 152.8μW Single-Chip Fully Synthesizable Wired-Logic DNN Processor for Always-On 35 Voice Commands Recognition Application. VLSI Technology and Circuits Atsutake Kosuge, Rei Sumikawa, Yao-Chung Hsu, Kota Shiba, Mototsugu Hamada, Tadahiro Kuroda
2023	J	`jnl`	A 7-nm FinFET 1.2-TB/s/mm IEEE J. Solid State Circuits Kota Shiba, Mitsuji Okada, Atsutake Kosuge, Mototsugu Hamada, Tadahiro Kuroda
2023	—	`conf`	A Fully Synthesized 13.7μJ/Prediction 88% Accuracy CIFAR-10 Single-Chip Data-Reusing Wired-Logic Processor Using Non-Linear Neural Network. ASP-DAC Yao-Chung Hsu, Atsutake Kosuge, Rei Sumikawa, Kota Shiba, Mototsugu Hamada, Tadahiro Kuroda
2023	C	`conf`	An Occlusion-Resilient mmWave Imaging Radar-Based Object Recognition System Using Synthetic Training Data Generation Technique. IECON Eitaro Kobayashi, Atsutake Kosuge, Mototsugu Hamada, Tadahiro Kuroda
2023	—	`conf`	Analysis and Design of a 7 Gb/s Rotatable Non-contact Connector with Grid Array Package Application. NEWCAS Ximing Wang, Atsutake Kosuge, Yasuhiro Hayashi, Kota Shiba, Mototsugu Hamada, Tadahiro Kuroda
2023	J	`jnl`	Crosstalk Analysis and Countermeasures of High-Bandwidth 3D-Stacked Memory Using Multi-Hop Inductive Coupling Interface. IEICE Trans. Electron. Kota Shiba, Atsutake Kosuge, Mototsugu Hamada, Tadahiro Kuroda
2023	J	`jnl`	Guest Editorial Introduction to the Special Issue on the 2022 Symposium on VLSI Circuits. IEEE J. Solid State Circuits Borivoje Nikolic, Mototsugu Hamada
2023	J	`jnl`	Polyomino: A 3D-SRAM-Centric Accelerator for Randomly Pruned Matrix Multiplication With Simple Reordering Algorithm and Efficient Compression Format in 180-nm CMOS. IEEE Trans. Circuits Syst. I Regul. Pap. Kota Shiba, Mitsuji Okada, Atsutake Kosuge, Mototsugu Hamada, Tadahiro Kuroda
2022	J	`jnl`	A 0.61-μJ/Frame Pipelined Wired-logic DNN Processor in 16-nm FPGA Using Convolutional Non-Linear Neural Network. IEEE Open J. Circuits Syst. Atsutake Kosuge, Yao-Chung Hsu, Mototsugu Hamada, Tadahiro Kuroda
2022	—	`conf`	A 13.7μJ/prediction 88% Accuracy CIFAR-10 Single-Chip Wired-logic Processor in 16-nm FPGA using Non-Linear Neural Network. HCS Yao-Chung Hsu, Atsutake Kosuge, Rei Sumikawa, Kota Shiba, Mototsugu Hamada, Tadahiro Kuroda
2022	—	`conf`	A 5.2GHz RFID Chip Contactlessly Mountable on FPC at any 90-Degree Rotation and Face Orientation. ASP-DAC Reiji Miura, Saito Shibata, Masahiro Usui, Atsutake Kosuge, Mototsugu Hamada, Tadahiro Kuroda
2022	J	`jnl`	A 6-Gb/s Inductively-Powered Non-Contact Connector With Rotatable Transmission Line Coupler and Interface Bridge IC. IEEE J. Solid State Circuits Atsutake Kosuge, Mototsugu Hamada, Tadahiro Kuroda
2022	J	`jnl`	A 6.5Gb/s Shared Bus Using Electromagnetic Connectors for Downsizing and Lightening Satellite Processor System. IEICE Trans. Fundam. Electron. Commun. Comput. Sci. Atsutake Kosuge, Mototsugu Hamada, Tadahiro Kuroda
2022	—	`conf`	A 7 Gb/s Micro Rotatable Transmission Line Coupler with Deep Proximity Coupling Mode and Ground Shielding Vias. ICECS 2022 Ximing Wang, Atsutake Kosuge, Yasuhiro Hayashi, Mototsugu Hamada, Tadahiro Kuroda
2022	—	`conf`	A 7-nm FinFET 1.2-TB/s/mm HCS Kota Shiba, Mitsuji Okada, Atsutake Kosuge, Mototsugu Hamada, Tadahiro Kuroda
2022	—	`conf`	A Low-power RFID with 100kbps Data Rate Employing High-speed Power Clock Generator for Complementary Pass-transistor Adiabatic Logic. ICECS 2022 Saito Shibata, Yoshiki Sawabe, Kota Shiba, Atsutake Kosuge, Mototsugu Hamada, Tadahiro Kuroda
2022	B	`conf`	An Anomaly Detection System for Transparent Objects Using Polarized-Image Fusion Technique. SAS Lixing Yu, Atsutake Kosuge, Mototsugu Hamada, Tadahiro Kuroda
2022	—	`conf`	Polyomino: A 3D-SRAM-Centric Architecture for Randomly Pruned Matrix Multiplication with Simple Rearrangement Algorithm and x0.37 Compression Format. NEWCAS Kota Shiba, Mitsuji Okada, Atsutake Kosuge, Mototsugu Hamada, Tadahiro Kuroda
2022	J	`jnl`	mmWave-YOLO: A mmWave Imaging Radar-Based Real-Time Multiclass Object Recognition System for ADAS Applications. IEEE Trans. Instrum. Meas. Atsutake Kosuge, Satoshi Suehiro, Mototsugu Hamada, Tadahiro Kuroda
2021	J	`jnl`	A 16 nJ/Classification FPGA-Based Wired-Logic DNN Accelerator Using Fixed-Weight Non-Linear Neural Net. IEEE J. Emerg. Sel. Topics Circuits Syst. Atsutake Kosuge, Mototsugu Hamada, Tadahiro Kuroda
2021	—	`conf`	A 3D-Stacked SRAM Using Inductive Coupling Technology for AI Inference Accelerator in 40-nm CMOS. ASP-DAC Kota Shiba, Tatsuo Omori, Mototsugu Hamada, Tadahiro Kuroda
2021	—	`conf`	A 5-GHz 0.15-mm A-SSCC Saito Shibata, Reiji Miura, Yoshiki Sawabe, Kota Shiba, Atsutake Kosuge, Mototsugu Hamada, Tadahiro Kuroda
2021	J	`jnl`	A 96-MB 3D-Stacked SRAM Using Inductive Coupling With 0.4-V Transmitter, Termination Scheme and 12: 1 SerDes in 40-nm CMOS. IEEE Trans. Circuits Syst. I Regul. Pap. Kota Shiba, Tatsuo Omori, Kodai Ueyoshi, Shinya Takamaeda-Yamazaki, Masato Motomura, Mototsugu Hamada, Tadahiro Kuroda
2021	—	`conf`	CA2 area detection from hippocampal microscope images using deep learning. MWSCAS Shohei Morinaga, Tomoe Ishikawa, Masato Yasui, Mototsugu Hamada, Tadahiro Kuroda
2021	—	`conf`	Sub-10-μm Coil Design for Multi-Hop Inductive Coupling Interface. ASP-DAC Tatsuo Omori, Kota Shiba, Mototsugu Hamada, Tadahiro Kuroda
2020	C	`conf`	A 3D-Stacked SRAM using Inductive Coupling with Low-Voltage Transmitter and 12: 1 SerDes. ISCAS Kota Shiba, Tatsuo Omori, Kodai Ueyoshi, Kota Ando, Kazutoshi Hirose, Shinya Takamaeda-Yamazaki, Masato Motomura, Mototsugu Hamada, Tadahiro Kuroda
2020	—	`conf`	A 50 Mbps/pin 12-input/output 40 nsec Latency Wireless Connector Using a Transmission Line Coupler with Compact SERDES IC in 180 nm CMOS. ICECS Kohei Ando, Kazuhisa Akatsuka, Chaoran Cheng, Tomoya Arakawa, Kota Shiba, Mototsugu Hamada, Tadahiro Kuroda
2020	J	`jnl`	Introduction to the Special Section on the 2019 Asian Solid-State Circuits Conference (A-SSCC). IEEE J. Solid State Circuits Atsushi Kawasumi, Mototsugu Hamada, Po-Hung Chen
2019	C	`conf`	Live Demonstration: A Non-Contact Transmission Line Connector for USB3.1 HD-Video Streaming. ISCAS Tomoya Arakawa, Joshin Sone, Mitsuji Okada, Mototsugu Hamada, Tadahiro Kuroda
2019	J	`jnl`	QUEST: Multi-Purpose Log-Quantized DNN Inference Engine Stacked on 96-MB 3-D SRAM Using Inductive Coupling Technology in 40-nm CMOS. IEEE J. Solid State Circuits Kodai Ueyoshi, Kota Ando, Kazutoshi Hirose, Shinya Takamaeda-Yamazaki, Mototsugu Hamada, Tadahiro Kuroda, Masato Motomura
2019	J	`jnl`	Transmission Line Coupler: High-Speed Interface for Non-Contact Connecter. IEICE Trans. Electron. Mototsugu Hamada, Tadahiro Kuroda
2018	—	`conf`	Balanced Mini-Batch Training for Imbalanced Image Data Classification with Neural Network. AI4I Ryota Shimizu, Kosuke Asako, Hiroki Ojima, Shohei Morinaga, Mototsugu Hamada, Tadahiro Kuroda
2018	—	`conf`	Comparative Performance Analysis of Dual-Rail Domino Logic and CMOS Logic Under NearThreshold Operation. MWSCAS Tsuyoshi Maruyama, Mototsugu Hamada, Tadahiro Kuroda
2018	C	`conf`	Design Methodology in Wireless Power Transfer System for 3-D Stacked Multiple Receivers. ISCAS Shusuke Yanagawa, Ryota Shimizu, Mototsugu Hamada, Toru Shimizu, Tadahiro Kuroda
2018	—	`conf`	Fully Integrated OOK-Powered Pad-Less Deep Sub-Wavelength-Sized 5-GHz RFID with On-Chip Antenna Using Adiabatic Logic in 0.18μM CMOS. VLSI Circuits Yuta Toeda, Takumi Fujimaki, Mototsugu Hamada, Tadahiro Kuroda
2018	J	`jnl`	Optimization of Resonant Capacitance in Wireless Power Transfer System with 3-D Stacked Two Receivers. IEICE Trans. Electron. Shusuke Yanagawa, Ryota Shimizu, Mototsugu Hamada, Toru Shimizu, Tadahiro Kuroda
2018	—	`conf`	QUEST: A 7.49TOPS multi-purpose log-quantized DNN inference engine stacked on 96MB 3D SRAM using inductive-coupling technology in 40nm CMOS. ISSCC Kodai Ueyoshi, Kota Ando, Kazutoshi Hirose, Shinya Takamaeda-Yamazaki, Junichiro Kadomoto, Tomoki Miyata, Mototsugu Hamada, Tadahiro Kuroda, Masato Motomura
2018	—	`conf`	Wireless Power Transfer System for 3-D stacked Multiple Receivers Switching between Single and Dual Frequency Modes. MWSCAS Shusuke Yanagawa, Ryota Shimizu, Mototsugu Hamada, Tadahiro Kuroda
2017	—	`conf`	Convolutional neural network for industrial egg classification. ISOCC Ryota Shimizu, Shusuke Yanagawa, Toru Shimizu, Mototsugu Hamada, Tadahiro Kuroda
2017	—	`conf`	Wireless power transfer to stacked modules for IoT sensor nodes. ISOCC Shusuke Yanagawa, Ryota Shimizu, Mototsugu Hamada, Toru Shimizu, Tadahiro Kuroda
2016	—	`conf`	Deep learning application trial to lung cancer diagnosis for medical sensor systems. ISOCC Ryota Shimizu, Shusuke Yanagawa, Yasutaka Monde, Hiroki Yamagishi, Mototsugu Hamada, Toru Shimizu, Tadahiro Kuroda
2014	—	`conf`	4.1 A 3-phase digitally controlled DC-DC converter with 88% ripple reduced 1-cycle phase adding/dropping scheme and 28% power saving CT/DT hybrid current control. ISSCC Chen Kong Teh, Atsushi Suzuki, Manabu Yamada, Mototsugu Hamada, Yasuo Unekawa
2012	J	`jnl`	A-104 dBc/Hz In-Band Phase Noise 3 GHz All Digital PLL with Phase Interpolation Based Hierarchical Time to Digital Converter. IEICE Trans. Electron. Daisuke Miyashita, Hiroyuki Kobayashi, Jun Deguchi, Shouhei Kousai, Mototsugu Hamada, Ryuichi Fujimoto
2011	J	`jnl`	A 40 nm 222 mW H.264 Full-HD Decoding, 25 Power Domains, 14-Core Application Processor With x512b Stacked DRAM. IEEE J. Solid State Circuits Yu Kikuchi, Makoto Takahashi, Tomohisa Maeda, Masatoshi Fukuda, Yasuhiro Koshio, Hiroyuki Hara, Hideho Arakida, Hideaki Yamamoto, Yousuke Hagiwara, Tetsuya Fujita, Manabu Watanabe, Hirokazu Ezawa, Takayoshi Shimazawa, Yasuo Ohara, Takashi Miyamori, Mototsugu Hamada, Masafumi Takahashi, Yukihito Oowaki
2011	—	`conf`	A 77% energy-saving 22-transistor single-phase-clocking D-flip-flop with adaptive-coupling configuration in 40nm CMOS. ISSCC Chen Kong Teh, Tetsuya Fujita, Hiroyuki Hara, Mototsugu Hamada
2011	J	`jnl`	A Low-Noise and Highly-Linear Transmitter with Envelope Injection Pre-Power Amplifier for Multi-Mode Radio. IEICE Trans. Fundam. Electron. Commun. Comput. Sci. Shouhei Kousai, Daisuke Miyashita, Junji Wadatsumi, Rui Ito, Takahiro Sekiguchi, Mototsugu Hamada, Kenichi Okada
2011	—	`conf`	An all-digital 8-DPSK polar transmitter with second-order approximation scheme and phase rotation-constant digital PA for bluetooth EDR in 65nm CMOS. ISSCC Hiroyuki Kobayashi, Shouhei Kousai, Yoshiaki Yoshihara, Mototsugu Hamada
2010	J	`jnl`	A 0.13 µm CMOS Bluetooth EDR Transceiver with High Sensitivity over Wide Temperature Range and Immunity to Process Variation. IEICE Trans. Electron. Kenichi Agawa, Shin-ichiro Ishizuka, Hideaki Majima, Hiroyuki Kobayashi, Masayuki Koizumi, Takeshi Nagano, Makoto Arai, Yutaka Shimizu, Asuka Maki, Go Urakawa, Tadashi Terada, Nobuyuki Itoh, Mototsugu Hamada, Fumie Fujii, Tadamasa Kato, Sadayuki Yoshitomi, Nobuaki Otsuka
2010	—	`conf`	A 222mW H.264 Full-HD decoding application processor with x512b stacked DRAM in 40nm. ISSCC Yu Kikuchi, Makoto Takahashi, Tomohisa Maeda, Hiroyuki Hara, Hideho Arakida, Hideaki Yamamoto, Yousuke Hagiwara, Tetsuya Fujita, Manabu Watanabe, Takayoshi Shimazawa, Yasuo Ohara, Takashi Miyamori, Mototsugu Hamada, Yukihito Oowaki
2010	J	`jnl`	A Fully Integrated 2 ˟ 1 Dual-Band Direct-Conversion Mobile WiMAX Transceiver With Dual-Mode Fractional Divider and Noise-Shaping Transimpedance Amplifier in 65 nm CMOS. IEEE J. Solid State Circuits Jun Deguchi, Daisuke Miyashita, Yosuke Ogasawara, Gaku Takemura, Masaomi Iwanaga, Kenichi Sami, Rui Ito, Junji Wadatsumi, Yuki Tsuda, Shoko Oda, Shunji Kawaguchi, Nobuyuki Itoh, Mototsugu Hamada
2010	—	`conf`	A fully integrated 2×1 dual-band direct-conversion transceiver with dual-mode fractional divider and noise-shaping TIA for mobile WiMAX SoC in 65nm CMOS. ISSCC Jun Deguchi, Daisuke Miyashita, Yosuke Ogasawara, Gaku Takemura, Masaomi Iwanaga, Kenichi Sami, Rui Ito, Junji Wadatsumi, Yuki Tsuda, Shoko Oda, Shunji Kawaguchi, Nobuyuki Itoh, Mototsugu Hamada
2009	—	`conf`	A 0.6V 380µW -14dBm LO-input 2.4GHz double-balanced current-reusing single-gate CMOS mixer with cyclic passive combiner. ISSCC Jun Deguchi, Daisuke Miyashita, Mototsugu Hamada
2009	—	`conf`	A 90nm CMOS CT BPF for Bluetooth transceivers with DT 1b-switched-resistor cutoff-frequency control. ISSCC Hideaki Majima, Mototsugu Hamada
2009	J	`jnl`	A Novel Automatic Quality Factor Tuning Scheme for a Low-Power Wideband Active-RC Filter. IEICE Trans. Fundam. Electron. Commun. Comput. Sci. Shouhei Kousai, Mototsugu Hamada, Rui Ito, Tetsuro Itakura
2009	—	`conf`	RF-analog circuit design in scaled SoC. ASP-DAC Nobuyuki Itoh, Mototsugu Hamada
2008	—	`conf`	A 1.2V 0.2-to-6.3GHz Transceiver with Less Than -29.5dB EVM@-3dBm and a Choke/Coil-Less Pre-Power Amplifier. ISSCC Shouhei Kousai, Daisuke Miyashita, Junji Wadatsumi, Asuka Maki, Takahiro Sekiguchi, Rui Ito, Mototsugu Hamada
2008	—	`conf`	A 9.7mW AAC-Decoding, 620mW H.264 720p 60fps Decoding, 8-Core Media Processor with Embedded Forward-Body-Biasing and Power-Gating Circuit in 65nm CMOS Technology. ISSCC Shuou Nomura, Fumihiko Tachibana, Tetsuya Fujita, Chen Kong Teh, Hiroyuki Usui, Fumiyuki Yamane, Yukimasa Miyamoto, Chaiyasit Kumtornkittikul, Hiroyuki Hara, Takahiro Yamashita, Jun Tanabe, Masaru Uchiyama, Yoshiro Tsuboi, Takashi Miyamori, Takeshi Kitahara, Hironori Sato, Y. Homma, Shuuji Matsumoto, Keiko Seki, Y. Watanabe, Mototsugu Hamada, Makoto Takahashi
2008	—	`conf`	A process variation compensation scheme using cell-based forward body-biasing circuits usable for 1.2V design. CICC Fumihiko Tachibana, Hironori Sato, Takahiro Yamashita, Hiroyuki Hara, Takeshi Kitahara, Shuou Nomura, Fumiyuki Yamane, Yoshiro Tsuboi, Keiko Seki, Shuuji Matsumoto, Yoshinori Watanabe, Mototsugu Hamada
2008	—	`conf`	Architectures and Circuit Techniques for Nanoscale RF CMOS (Forum). ISSCC Stefan Heinen, Francesco Svelto, Jan Craninckx, Mototsugu Hamada, Domine Leenaerts, Chris Rudell
2007	—	`conf`	A -90 dBm sensitivity 0.13 μm CMOS bluetooth transceiver operating in wide temperature range. CICC Kenichi Agawa, Hideaki Majima, Hiroyuki Kobayashi, Masayuki Koizumi, Shin-ichiro Ishizuka, Takeshi Nagano, Makoto Arai, Yutaka Shimizu, Go Urakawa, Nobuyuki Itoh, Mototsugu Hamada, Nobuaki Otsuka
2007	J	`jnl`	A 19.7 MHz, Fifth-Order Active-RCChebyshev LPF for Draft IEEE802.11n With Automatic Quality-Factor Tuning Scheme. IEEE J. Solid State Circuits Shouhei Kousai, Mototsugu Hamada, Rui Ito, Tetsuro Itakura
2007	—	`conf`	A novel quality factor tuning scheme for active-RC filters. ESSCIRC Shouhei Kousai, Mototsugu Hamada, Rui Ito, Tetsuro Itakura
2007	C	`conf`	An automated runtime power-gating scheme. ICCD Mototsugu Hamada, Takeshi Kitahara, Naoyuki Kawabe, Hironori Sato, Tsuyoshi Nishikawa, Takayoshi Shimazawa, Takahiro Yamashita, Hiroyuki Hara, Yukihito Oowaki
2007	—	`conf`	WLAN/Bluetooth. ISSCC George Chien, Mototsugu Hamada
2006	J	`jnl`	A 63-mW H.264/MPEG-4 audio/visual codec LSI with module-wise dynamic Voltage/frequency scaling. IEEE J. Solid State Circuits Toshihide Fujiyoshi, Shinichiro Shiratake, Shuou Nomura, Tsuyoshi Nishikawa, Yoshiyuki Kitasho, Hideho Arakida, Yuji Okuda, Yoshiro Tsuboi, Mototsugu Hamada, Hiroyuki Hara, Tetsuya Fujita, Fumitoshi Hatori, Takayoshi Shimazawa, Kunihiko Yahagi, Hideki Takeda, Masami Murakata, Fumihiro Minami, Naoyuki Kawabe, Takeshi Kitahara, Katsuhiro Seta, Masafumi Takahashi, Yukihito Oowaki, Tohru Furuyama
2006	J	`jnl`	Conditional Data Mapping Flip-Flops for Low-Power and High-Performance Systems. IEEE Trans. Very Large Scale Integr. Syst. Chen Kong Teh, Mototsugu Hamada, Tetsuya Fujita, Hiroyuki Hara, N. Ikumi, Yukihito Oowaki
2006	J	`jnl`	Module-Wise Dynamic Voltage and Frequency Scaling for a 90 nm H.264/MPEG-4 Codec LSI. IEICE Trans. Electron. Yukihito Oowaki, Shinichiro Shiratake, Toshihide Fujiyoshi, Mototsugu Hamada, Fumitoshi Hatori, Masami Murakata, Masafumi Takahashi
2005	—	`conf`	A 1.2-V CMOS complex bandpass filter with a tunable center frequency. ESSCIRC Hideaki Majima, Hiroki Ishikuro, Kenichi Agawa, Mototsugu Hamada
2005	J	`jnl`	A 17-mW 0.66-mm IEEE J. Solid State Circuits Shwetabh Verma, Junfeng Xu, Mototsugu Hamada, Thomas H. Lee
2005	—	`conf`	A conditional clocking flip-flop for low power H.264/MPEG-4 audio/visual codec LSI. CICC Mototsugu Hamada, Hiroyuki Hara, Tetsuya Fujita, Chen Kong Teh, Takayoshi Shimazawa, Naoyuki Kawabe, Takeshi Kitahara, Yu Kikuchi, Tsuyoshi Nishikawa, Makoto Takahashi, Yukihito Oowaki
2005	—	`conf`	A phase noise minimization of CMOS VCOs over wide tuning range and large PVT variations. CICC Daisuke Miyashita, Hiroki Ishikuro, Shouhei Kousai, Hiroyuki Kobayashi, Hideaki Majima, Kenichi Agawa, Mototsugu Hamada
2001	—	`conf`	Utilizing surplus timing for power reduction. CICC Mototsugu Hamada, Yukio Ootaguro, Tadahiro Kuroda
2000	J	`jnl`	A 60-MHz 240-mW MPEG-4 videophone LSI with 16-Mb embedded DRAM. IEEE J. Solid State Circuits Masafumi Takahashi, Tsuyoshi Nishikawa, Mototsugu Hamada, Toshinari Takayanagi, Hideho Arakida, Noriaki Machida, Hideaki Yamamoto, Toshihide Fujiyoshi, Yoko Ohashi, Osamu Yamagishi, Tatsuo Samata, Atsushi Asano, Toshihiro Terazawa, Kenji Ohmori, Yoshinori Watanabe, Hiroki Nakamura, Shigenobu Minami, Tadahiro Kuroda, Tohru Furuyama
2000	J	`jnl`	Low-power CMOS digital design with dual embedded adaptive power supplies. IEEE J. Solid State Circuits Tadahiro Kuroda, Mototsugu Hamada
1998	J	`jnl`	A 60-mW MPEG4 video codec using clustered voltage scaling with variable supply-voltage scheme. IEEE J. Solid State Circuits Masafumi Takahashi, Mototsugu Hamada, Tsuyoshi Nishikawa, Hideho Arakida, Tetsuya Fujita, Fumitoshi Hatori, Shinji Mita, Kojiro Suzuki, Akihiko Chiba, Toshihiro Terazawa, Fumihiko Sano, Yoshinori Watanabe, Kimiyoshi Usami, Mutsunori Igarashi, Takashi Ishikawa, Masahiro Kanazawa, Tadahiro Kuroda, Tohru Furuyama
1998	—	`conf`	A top-down low power design technique using clustered voltage scaling with variable supply-voltage scheme. CICC Mototsugu Hamada, Masafumi Takahashi, Hideho Arakida, Akihiko Chiba, Toshihiro Terazawa, Takashi Ishikawa, Masahiro Kanazawa, Mutsunori Igarashi, Kimiyoshi Usami, Tadahiro Kuroda
1998	A*	`conf`	Design Methodology of Ultra Low-Power MPEG4 Codec Core Exploiting Voltage Scaling Techniques. DAC Kimiyoshi Usami, Mutsunori Igarashi, Takashi Ishikawa, Masahiro Kanazawa, Masafumi Takahashi, Mototsugu Hamada, Hideho Arakida, Toshihiro Terazawa, Tadahiro Kuroda