Morteza Saheb Zamani

108 papers A 5B 3C 16Misc 4Journal 51Unranked 29

Year	Rank	Type	Title / Venue / Authors
2025	J	`jnl`	A Scalable Synthesis Algorithm for Reversible Functions. CoRR Moein Sarvaghad-Moghaddam, Morteza Saheb Zamani, Mehdi Sedighi
2025	J	`jnl`	A parallel computational approach for energy-efficient hydraulic analysis of water distribution networks using learning automata. Sustain. Comput. Informatics Syst. Ali Suvizi, Ruhollah Ahmadi, Morteza Saheb Zamani, Mohammad Reza Meybodi
2023	J	`jnl`	A parallel computing architecture based on cellular automata for hydraulic analysis of water distribution networks. J. Parallel Distributed Comput. Ali Suvizi, Azim Farghadan, Morteza Saheb Zamani
2023	J	`jnl`	An energy-efficient and accuracy-aware edge computing framework for heart arrhythmia detection: A joint model selection and task offloading approach. J. Supercomput. Vahid Amini, Mahmoud Momtazpour, Morteza Saheb Zamani
2023	J	`jnl`	Low-overhead code concatenation approaches for universal quantum computation. Quantum Inf. Process. Eesa Nikahd, Morteza Saheb Zamani, Mehdi Sedighi
2022	J	`jnl`	FIFA: A Fully Invertible FPGA Architecture to Reduce BTI-Induced Aging Effects. IEEE Trans. Computers Mohammad Hadi Mottaghi, Mehdi Sedighi, Morteza Saheb Zamani
2022	J	`jnl`	Runtime hardware Trojan detection by reconfigurable monitoring circuits. J. Supercomput. Reza Fani, Morteza Saheb Zamani
2021	J	`jnl`	Real-Time Activity Recognition and Intention Recognition Using a Vision-based Embedded System. CoRR Sahar Darafsh, Saeed Shiry Ghidary, Morteza Saheb Zamani
2020	J	`jnl`	A system architecture for parallel analysis of flux-balanced metabolic pathways. Comput. Biol. Chem. Mona Arabzadeh, Mehdi Sedighi, Morteza Saheb Zamani, Sayed-Amir Marashi
2020	J	`jnl`	Aging Mitigation in FPGAs Considering Delay, Power, and Temperature. IEEE Trans. Reliab. Mohammad Hadi Mottaghi, Mehdi Sedighi, Morteza Saheb Zamani
2020	J	`jnl`	Combinational Counters: A Low Overhead Approach to Address DPA Attacks. J. Circuits Syst. Comput. Ghobad Zarrinchian, Morteza Saheb Zamani
2018	J	`jnl`	A graph-based approach to analyze flux-balanced pathways in metabolic networks. Biosyst. Mona Arabzadeh, Morteza Saheb Zamani, Mehdi Sedighi, Sayed-Amir Marashi
2017	J	`jnl`	Geometry-Based Optimization of One-Way Quantum Computation Measurement Patterns. CoRR Maryam Eslamy, Mahboobeh Houshmand, Morteza Saheb Zamani, Mehdi Sedighi
2017	J	`jnl`	Latch-Based Structure: A High Resolution and Self-Reference Technique for Hardware Trojan Detection. IEEE Trans. Computers Ghobad Zarrinchian, Morteza Saheb Zamani
2017	J	`jnl`	Quantum Circuit Synthesis Targeting to Improve One-Way Quantum Computation Pattern Cost Metrics. ACM J. Emerg. Technol. Comput. Syst. Mahboobeh Houshmand, Mehdi Sedighi, Morteza Saheb Zamani, Kourosh Marjoei
2016	J	`jnl`	FogLight: an efficient matrix-based approach to construct metabolic pathways by search space reduction. Bioinform. Mehrshad Khosraviani, Morteza Saheb Zamani, Gholamreza Bidkhori
2016	J	`jnl`	One-Way Quantum Computer Simulation. CoRR Eesa Nikahd, Mahboobeh Houshmand, Morteza Saheb Zamani, Mehdi Sedighi
2016	J	`jnl`	Quantum-Logic Synthesis of Hermitian Gates. ACM J. Emerg. Technol. Comput. Syst. Mona Arabzadeh, Mahboobeh Houshmand, Mehdi Sedighi, Morteza Saheb Zamani
2015	J	`jnl`	A Trust-Driven Placement Approach: A New Perspective on Design for Hardware Trust. J. Circuits Syst. Comput. Seyed Mohammad Hossein Shekarian, Morteza Saheb Zamani
2015	J	`jnl`	GA-based approach to find the stabilizers of a given sub-space. Genet. Program. Evolvable Mach. Mahboobeh Houshmand, Morteza Saheb Zamani, Mehdi Sedighi, Monireh Houshmand
2015	J	`jnl`	Improving hardware Trojan detection by retiming. Microprocess. Microsystems Seyed Mohammad Hossein Shekarian, Morteza Saheb Zamani
2015	J	`jnl`	One-way quantum computer simulation. Microprocess. Microsystems Eesa Nikahd, Mahboobeh Houshmand, Morteza Saheb Zamani, Mehdi Sedighi
2014	J	`jnl`	A study on the efficiency of hardware Trojan detection based on path-delay fingerprinting. Microprocess. Microsystems Arash Nejat, Seyed Mohammad Hossein Shekarian, Morteza Saheb Zamani
2014	J	`jnl`	Automatic translation of quantum circuits to optimized one-way quantum computation patterns. Quantum Inf. Process. Mahboobeh Houshmand, Morteza Saheb Zamani, Mehdi Sedighi, Mohammad Hossein Samavatian
2014	J	`jnl`	Decomposition of Diagonal Hermitian Quantum Gates Using Multiple-Controlled Pauli Z Gates. CoRR Mahboobeh Houshmand, Morteza Saheb Zamani, Mehdi Sedighi, Mona Arabzadeh
2014	J	`jnl`	Decomposition of Diagonal Hermitian Quantum Gates Using Multiple-Controlled Pauli Z Gates. ACM J. Emerg. Technol. Comput. Syst. Mahboobeh Houshmand, Morteza Saheb Zamani, Mehdi Sedighi, Mona Arabzadeh
2014	J	`jnl`	Quantum circuit physical design methodology with emphasis on physical synthesis. Quantum Inf. Process. Naser MohammadZadeh, Morteza Saheb Zamani, Mehdi Sedighi
2013	J	`jnl`	A Quantum Physical Design Flow Using ILP and Graph Drawing. CoRR Maryam Yazdani, Morteza Saheb Zamani, Mehdi Sedighi
2013	J	`jnl`	A quantum physical design flow using ILP and graph drawing. Quantum Inf. Process. Maryam Yazdani, Morteza Saheb Zamani, Mehdi Sedighi
2013	J	`jnl`	Depth-optimized reversible circuit synthesis. Quantum Inf. Process. Mona Arabzadeh, Morteza Saheb Zamani, Mehdi Sedighi, Mehdi Saeedi
2013	A	`conf`	Improving bitstream compression by modifying FPGA architecture. FPGA Seyyed Ahmad Razavi, Morteza Saheb Zamani
2012	J	`jnl`	Depth-Optimized Reversible Circuit Synthesis. CoRR Mona Arabzadeh, Morteza Saheb Zamani, Mehdi Sedighi, Mehdi Saeedi
2012	C	`conf`	Hardware Acceleration of STON Algorithm for Comparing 3-D Structure of Proteins. DSD Somayeh Kashi, Morteza Saheb Zamani
2012	C	`conf`	OWQS: One-Way Quantum Computation Simulator. DSD Eesa Nikahd, Mahboobeh Houshmand, Morteza Saheb Zamani, Mehdi Sedighi
2012	A	`conf`	Timing yield improvement of FPGAs utilizing enhanced architectures and multiple configurations under process variation (abstract only). FPGA Fatemeh Sadat Pourhashemi, Morteza Saheb Zamani
2011	J	`jnl`	Auxiliary qubit selection: a physical synthesis technique for quantum circuits. Quantum Inf. Process. Naser MohammadZadeh, Morteza Saheb Zamani, Mehdi Sedighi
2011	J	`jnl`	Block-based quantum-logic synthesis. Quantum Inf. Comput. Mehdi Saeedi, Mona Arabzadeh, Morteza Saheb Zamani, Mehdi Sedighi
2011	—	`conf`	Evaluation of FPGA routing architectures under process variation. ACM Great Lakes Symposium on VLSI Fatemeh Sadat Pourhashemi, Morteza Saheb Zamani
2011	J	`jnl`	Improved predictability, timing yield and power consumption using hierarchical highways-on-chip planning methodology. Integr. Ali Jahanian, Morteza Saheb Zamani, Hamid Safizadeh
2011	J	`jnl`	Mitigating soft errors in SRAM-based FPGAs by decoding configuration bits in switch boxes. Microelectron. J. Hassan Ebrahimi, Morteza Saheb Zamani, Hamid R. Zarandi
2011	—	`conf`	TSV reduction in homogeneous 3D FPGAs by logic resource and input pad replication. 3DIC Seyyed Hasan Moallempour, Seyyed Ahmad Razavi, Morteza Saheb Zamani
2011	C	`conf`	VMAP: A Variation Map-Aware Placement Algorithm for Leakage Power Reduction in FPGAs. DSD Behzad Salami, Morteza Saheb Zamani, Ali Jahanian
2010	J	`jnl`	A Library-Based Synthesis Methodology for Reversible Logic. CoRR Mehdi Saeedi, Mehdi Sedighi, Morteza Saheb Zamani
2010	—	`conf`	A Switch Box Architecture to Mitigate Bridging and Short Faults in SRAM-Based FPGAs. DFT Hassan Ebrahimi, Morteza Saheb Zamani, Seyyed Ahmad Razavi
2010	—	`conf`	A decoder-based switch box to mitigate soft errors in SRAM-based FPGAs. ASP-DAC Hassan Ebrahimi, Morteza Saheb Zamani, Hamid R. Zarandi
2010	J	`jnl`	A library-based synthesis methodology for reversible logic. Microelectron. J. Mehdi Saeedi, Mehdi Sedighi, Morteza Saheb Zamani
2010	J	`jnl`	Block-based quantum-logic synthesis. CoRR Mehdi Saeedi, Mona Arabzadeh, Morteza Saheb Zamani, Mehdi Sedighi
2010	J	`jnl`	Early Buffer Planning with Congestion Control Using Buffer Requirement Map. J. Circuits Syst. Comput. Ali Jahanian, Morteza Saheb Zamani
2010	J	`jnl`	Quantum physical synthesis: Improving physical design by netlist modifications. Microelectron. J. Naser MohammadZadeh, Mehdi Sedighi, Morteza Saheb Zamani
2010	C	`conf`	Reduction of process variation effect on FPGAs using multiple configurations. VLSI-SoC Delasa Aghamirzaie, Seyyed Ahmad Razavi, Morteza Saheb Zamani, Mahdi Nabiyouni
2010	J	`jnl`	Reversible Circuit Synthesis Using a Cycle-Based Approach. CoRR Mehdi Saeedi, Morteza Saheb Zamani, Mehdi Sedighi, Zahra Sasanian
2010	J	`jnl`	Reversible circuit synthesis using a cycle-based approach. ACM J. Emerg. Technol. Comput. Syst. Mehdi Saeedi, Morteza Saheb Zamani, Mehdi Sedighi, Zahra Sasanian
2010	J	`jnl`	Rule-Based Optimization of Reversible Circuits. CoRR Mona Arabzadeh, Mehdi Saeedi, Morteza Saheb Zamani
2010	—	`conf`	Rule-based optimization of reversible circuits. ASP-DAC Mona Arabzadeh, Mehdi Saeedi, Morteza Saheb Zamani
2009	—	`conf`	A cycle-based synthesis algorithm for reversible logic. ASP-DAC Zahra Sasanian, Mehdi Saeedi, Mehdi Sedighi, Morteza Saheb Zamani
2009	—	`conf`	A tileable switch module architecture for homogeneous 3D FPGAs. 3DIC Seyyed Ahmad Razavi, Morteza Saheb Zamani, Kia Bazargan
2009	—	`conf`	Improved performance and yield with chip master planning design methodology. ACM Great Lakes Symposium on VLSI Ali Jahanian, Morteza Saheb Zamani
2009	C	`conf`	Improving Latency of Quantum Circuits by Gate Exchanging. DSD Naser MohammadZadeh, Morteza Saheb Zamani, Mehdi Sedighi
2009	A	`conf`	Multi-domain clock skew scheduling-aware register placement to optimize clock distribution network. DATE Naser MohammadZadeh, Minoo Mirsaeedi, Ali Jahanian, Morteza Saheb Zamani
2008	C	`conf`	A Fast Transformation-Based Synthesis Algorithm for Reversible Circuits. DSD Ehsan K. Ardestani, Morteza Saheb Zamani, Mehdi Sedighi
2008	Misc	`conf`	A Novel Crosstalk Estimator after Placement. CSICC Arash Mehdizadeh, Morteza Saheb Zamani
2008	J	`jnl`	A fast IP routing lookup architecture for multi-gigabit switching routers based on reconfigurable systems. Microprocess. Microsystems Hamid Fadishei, Mehdi Saeedi, Morteza Saheb Zamani
2008	—	`conf`	An Efficient Method to Estimate Crosstalk after Placement Incorporating a Reduction Scheme. ISVLSI Arash Mehdizadeh, Morteza Saheb Zamani, Hosein Shafiei
2008	C	`conf`	An Efficient Non-Tree Clock Routing Algorithm for Reducing Delay Uncertainty. DSD Morteza Saheb Zamani, Maryam Taajobian, Mehdi Saeedi
2008	J	`jnl`	An architecture framework for an adaptive extensible processor. J. Supercomput. Hamid Noori, Farhad Mehdipour, Kazuaki J. Murakami, Koji Inoue, Morteza Saheb Zamani
2008	—	`conf`	Design space exploration for a coarse grain accelerator. ASP-DAC Farhad Mehdipour, Hamid Noori, Morteza Saheb Zamani, Koji Inoue, Kazuaki J. Murakami
2008	Misc	`conf`	Evaluating the Metro-on-Chip Methodology to Improve the Congestion and Routability. CSICC Ali Jahanian, Morteza Saheb Zamani, Mostafa Rezvani, Mehrdad Najibi
2008	C	`conf`	Evaluation and Improvement of Quantum Synthesis Algorithms based on a Thorough Set of Metrics. DSD Mehdi Saeedi, Naser MohammadZadeh, Mehdi Sedighi, Morteza Saheb Zamani
2008	—	`conf`	FPGA-Based Circuit Model Emulation of Quantum Algorithms. ISVLSI Mahdi Aminian, Mehdi Saeedi, Morteza Saheb Zamani, Mehdi Sedighi
2008	—	`conf`	Moving forward: A non-search based synthesis method toward efficient CNOT-based quantum circuit synthesis algorithms. ASP-DAC Mehdi Saeedi, Morteza Saheb Zamani, Mehdi Sedighi
2008	C	`conf`	Multi-Objective Statistical Yield Enhancement using Evolutionary Algorithm. DSD Minoo Mirsaeedi, Morteza Saheb Zamani, Mehdi Saeedi
2008	—	`conf`	Performance Improvement of Physical Retiming with Shortcut Insertion. ISVLSI Adel Dokhanchi, Mostafa Rezvani, Ali Jahanian, Morteza Saheb Zamani
2008	C	`conf`	Performance and Timing Yield Enhancement using Highway-on-Chip Planning. DSD Ali Jahanian, Morteza Saheb Zamani
2008	C	`conf`	Proposing an efficient method to estimate and reduce crosstalk after placement in VLSI circuits. AICCSA Arash Mehdizadeh, Morteza Saheb Zamani
2008	—	`conf`	Shared-PPRM: A Memory-Efficient Representation for Boolean Reversible Functions. ISVLSI Yasaman Sanaee, Mehdi Saeedi, Morteza Saheb Zamani
2008	—	`conf`	Simultaneous Gate Sizing and Skew Scheduling to Statistical Yield Improvement. ISVLSI Minoo Mirsaeedi, Morteza Saheb Zamani, Mehdi Saeedi
2008	J	`jnl`	Synthesis of reversible circuits using a moving forward strategy. IEICE Electron. Express Mehdi Saeedi, Mehdi Sedighi, Morteza Saheb Zamani
2008	J	`jnl`	Using metro-on-chip in physical design flow for congestion and routability improvement. Microelectron. J. Ali Jahanian, Morteza Saheb Zamani
2007	A	`conf`	A novel synthesis algorithm for reversible circuits. ICCAD Mehdi Saeedi, Mehdi Sedighi, Morteza Saheb Zamani
2007	C	`conf`	Algebraic Characterization of CNOT-Based Quantum Circuits with its Applications on Logic Synthesis. DSD Mehdi Saeedi, Morteza Saheb Zamani, Mehdi Sedighi
2007	—	`conf`	An Efficient Analytical Approach to Path-Based Buffer Insertion. ISVLSI Hamid Reza Kheirabadi, Morteza Saheb Zamani, Mehdi Saeedi
2007	C	`conf`	An efficient heterogeneous reconfigurable functional unit for an adaptive dynamic extensible processor. VLSI-SoC Arash Mehdizadeh, Behnam Ghavami, Morteza Saheb Zamani, Hossein Pedram, Farhad Mehdipour
2007	—	`conf`	An efficient net ordering algorithm for buffer insertion. ACM Great Lakes Symposium on VLSI Hamid Reza Kheirabadi, Morteza Saheb Zamani
2007	J	`jnl`	Evaluation, prediction and reduction of routing congestion. Microelectron. J. Mehdi Saeedi, Morteza Saheb Zamani, Ali Jahanian
2007	—	`conf`	Handling Control Data Flow Graphs for a Tightly Coupled Reconfigurable Accelerator. ICESS Hamid Noori, Farhad Mehdipour, Morteza Saheb Zamani, Koji Inoue, Kazuaki J. Murakami
2007	—	`conf`	Improved timing closure by early buffer planning in floor-placement design flow. ACM Great Lakes Symposium on VLSI Ali Jahanian, Morteza Saheb Zamani
2007	J	`jnl`	Improving Performance and Energy Saving in a Reconfigurable Processor via Accelerating Control Data Flow Graphs. IEICE Trans. Inf. Syst. Farhad Mehdipour, Hamid Noori, Morteza Saheb Zamani, Koji Inoue, Kazuaki J. Murakami
2007	J	`jnl`	Metro-on-chip: an efficient physical design technique for congestion reduction. IEICE Electron. Express Ali Jahanian, Morteza Saheb Zamani
2007	—	`conf`	On the Behavior of Substitution-based Reversible Circuit Synthesis Algorithms: Investigation and Improvement. ISVLSI Mehdi Saeedi, Morteza Saheb Zamani, Mehdi Sedighi
2006	B	`conf`	A Reconfigurable Functional Unit for an Adaptive Dynamic Extensible Processor. FPL Hamid Noori, Farhad Mehdipour, Kazuaki J. Murakami, Koji Inoue, Morteza Saheb Zamani
2006	—	`conf`	An Integrated Temporal Partitioning and Mapping Framework for Handling Custom Instructions on a Reconfigurable Functional Unit. Asia-Pacific Computer Systems Architecture Conference Farhad Mehdipour, Hamid Noori, Morteza Saheb Zamani, Kazuaki J. Murakami, Mehdi Sedighi, Koji Inoue
2006	J	`jnl`	An integrated temporal partitioning and physical design framework for static compilation of reconfigurable computing systems. Microprocess. Microsystems Farhad Mehdipour, Morteza Saheb Zamani, Mehdi Sedighi
2006	C	`conf`	Custom Instruction Generation Using Temporal Partitioning Techniques for a Reconfigurable Functional Unit. EUC Farhad Mehdipour, Hamid Noori, Morteza Saheb Zamani, Kazuaki J. Murakami, Koji Inoue, Mehdi Sedighi
2006	—	`conf`	GifT: A Gravity-Directed and Life-Time Based Algorithm for Temporal Partitioning of Data Flow Graphs. ERSA Farhad Mehdipour, Morteza Saheb Zamani, Mehdi Sedighi, Kazuaki J. Murakami, Hamid Noori
2006	—	`conf`	Multi-Level Buffer Block Planning and Buffer Insertion for Large Design Circuits. ISVLSI Ali Jahanian, Morteza Saheb Zamani
2006	—	`conf`	Prediction and reduction of routing congestion. ISPD Mehdi Saeedi, Morteza Saheb Zamani, Ali Jahanian
2006	A	`conf`	Reducing reconfiguration time of reconfigurable computing systems in integrated temporal partitioning and physical design framework. IPDPS Farhad Mehdipour, Morteza Saheb Zamani, Hamid Reza Ahmadifar, Mehdi Sedighi, Kazuaki J. Murakami
2005	—	`conf`	A Reconfigurable Architecture for Implementing Multiple Cipher Algorithms. FPT Ali Valizadeh, Morteza Saheb Zamani, Babak Sadeghian, Farhad Mehdipour
2005	—	`conf`	A novel reconfigurable hardware architecture for IP address lookup. ANCS Hamid Fadishei, Morteza Saheb Zamani, Masoud Sabaei
2005	—	`conf`	Cellular Learning Automata based Evolutionary Computing (CLA-EC) for Intrinsic Hardware Evolution. Evolvable Hardware Arash Hariri, Reza Rastegar, Keivan Navi, Morteza Saheb Zamani, Mohammad Reza Meybodi
2005	Misc	`conf`	Parallel Hardware Implementation of Cellular Learning Automata Based Evolutionary Computing (CLA-EC) on FPGA. FCCM Arash Hariri, Reza Rastegar, Morteza Saheb Zamani, Mohammad Reza Meybodi
2005	C	`conf`	Reducing Inter-Configuration Memory Usage and Performance Improvement in Reconfigurable Computing Systems. DSD Farhad Mehdipour, Morteza Saheb Zamani, Mehdi Sedighi
2003	B	`conf`	Rectilinear floorplanning of FPGAs using Kohonen map. IJCNN Morteza Saheb Zamani, Masoud Soleimani
1999	B	`conf`	An efficient method for placement of VLSI designs with Kohonen map. IJCNN Morteza Saheb Zamani, Farhad Mehdipour
1995	Misc	`conf`	A New Neural Network Approach to the Floorplanning of Hierarchical VLSI Designs. IWANN Morteza Saheb Zamani, Graham R. Hellestrand
1995	C	`conf`	A Stepwise Refinement Algorithm for Integrated Floorplanning, Placement and Routing of Hierarchical Designs. ISCAS Morteza Saheb Zamani, Graham R. Hellestrand
1995	—	`conf`	A neural network approach to the placement problem. ASP-DAC Morteza Saheb Zamani, Graham R. Hellestrand
1995	—	`conf`	Placement with self-organising neural networks. ICNN Morteza Saheb Zamani, Graham R. Hellestrand