Morteza Fayazi

22 papers A 1C 1Journal 15Unranked 5
YearRankTypeTitle / Venue / Authors
2026 — conf
MuaLLM: A Multimodal Large Language Model Agent for Circuit Design Assistance with Hybrid Contextual Retrieval-Augmented Generation.
ASP-DAC
Pravallika Abbineni, Saoud Aldowaish, Colin Liechty, Soroosh Noorzad, Ali Ghazizadeh Ghalati, Morteza Fayazi
2026 J jnl
SINA: A Circuit Schematic Image-to-Netlist Generator Using Artificial Intelligence.
CoRR
Saoud Aldowaish, Yashwanth Karumanchi, Kai-Chen Chiang, Soroosh Noorzad, Morteza Fayazi
2025 J jnl
DAP: A 507-GMACs/J 256-Core Domain Adaptive Processor for Wireless Communication and Linear Algebra Kernels in 12-nm FINFET.
IEEE J. Solid State Circuits
Kuan-Yu Chen, Chi-Sheng Yang, Yu-Hsiu Sun, Chien-Wei Tseng, Morteza Fayazi, Xin He, Siying Feng, Yufan Yue, Trevor N. Mudge, Ronald G. Dreslinski, Hun-Seok Kim, David T. Blaauw
2025 J jnl
MuaLLM: A Multimodal Large Language Model Agent for Circuit Design Assistance with Hybrid Contextual Retrieval-Augmented Generation.
CoRR
Pravallika Abbineni, Saoud Aldowaish, Colin Liechty, Soroosh Noorzad, Ali Ghazizadeh, Morteza Fayazi
2024 J jnl
Canalis: A Throughput-Optimized Framework for Real-Time Stream Processing of Wireless Communication.
ACM Trans. Reconfigurable Technol. Syst.
Kuan-Yu Chen, Thomas Mason Nelson, Alireza Khadem, Morteza Fayazi, Sanjay Sri Vallabh Singapuram, Ronald G. Dreslinski, Nishil Talati, Hun-Seok Kim, David T. Blaauw
2023 — conf
A Compact CMOS 363 GHz Autodyne FMCW Radar with 57 GHz Bandwidth for Dental Imaging.
CICC
Morteza Tavakoli Taba, S. M. Hossein Naghavi, Morteza Fayazi, Ali Sadeghi, Andreia Cathelin, Ehsan Afshari
2023 J jnl
AnGeL: Fully-Automated Analog Circuit Generator Using a Neural Network Assisted Semi-Supervised Learning Approach.
IEEE Trans. Circuits Syst. I Regul. Pap.
Morteza Fayazi, Morteza Tavakoli Taba, Ehsan Afshari, Ronald G. Dreslinski
2023 A conf
FuNToM: Functional Modeling of RF Circuits Using a Neural Network Assisted Two-Port Analysis Method.
ICCAD
Morteza Fayazi, Morteza Tavakoli Taba, Amirata Tabatabavakili, Ehsan Afshari, Ronald G. Dreslinski
2023 J jnl
FuNToM: Functional Modeling of RF Circuits Using a Neural Network Assisted Two-Port Analysis Method.
CoRR
Morteza Fayazi, Morteza Tavakoli Taba, Amirata Tabatabavakili, Ehsan Afshari, Ronald G. Dreslinski
2023 J jnl
Open Information Extraction: A Review of Baseline Techniques, Approaches, and Applications.
CoRR
Serafina Kamp, Morteza Fayazi, Zineb Benameur-El Youbi, Shuyan Yu, Ronald G. Dreslinski
2022 — conf
A 507 GMACs/J 256-Core Domain Adaptive Systolic-Array-Processor for Wireless Communication and Linear-Algebra Kernels in 12nm FINFET.
VLSI Technology and Circuits
Kuan-Yu Chen, Chi-Sheng Yang, Yu-Hsiu Sun, Chien-Wei Tseng, Morteza Fayazi, Xin He, Siying Feng, Yufan Yue, Trevor N. Mudge, Ronald G. Dreslinski, Hun-Seok Kim, David T. Blaauw
2022 J jnl
FASCINET: A Fully Automated Single-Board Computer Generator Using Neural Networks.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst.
Morteza Fayazi, Zachary Colter, Zineb Benameur-El Youbi, Javad Bagherzadeh, Tutu Ajayi, Ronald G. Dreslinski
2022 J jnl
Tablext: A combined neural network and heuristic based table extractor.
Array
Zach Colter, Morteza Fayazi, Zineb Benameur-El Youbi, Serafina Kamp, Shuyan Yu, Ronald G. Dreslinski
2022 J jnl
Versa: A 36-Core Systolic Multiprocessor With Dynamically Reconfigurable Interconnect and Memory.
IEEE J. Solid State Circuits
Sung Kim, Morteza Fayazi, Alhad Daftardar, Kuan-Yu Chen, Jielun Tan, Subhankar Pal, Tutu Ajayi, Yan Xiong, Trevor N. Mudge, Chaitali Chakrabarti, David T. Blaauw, Ronald G. Dreslinski, Hun-Seok Kim
2021 J jnl
Applications of Artificial Intelligence on the Modeling and Optimization for Analog and Mixed-Signal Circuits: A Review.
IEEE Trans. Circuits Syst. I Regul. Pap.
Morteza Fayazi, Zachary Colter, Ehsan Afshari, Ronald G. Dreslinski
2021 J jnl
Tablext: A Combined Neural Network And Heuristic Based Table Extractor.
CoRR
Zach Colter, Morteza Fayazi, Zineb Benameur-El Youbi, Serafina Kamp, Shuyan Yu, Ronald G. Dreslinski
2021 — conf
Versa: A Dataflow-Centric Multiprocessor with 36 Systolic ARM Cortex-M4F Cores and a Reconfigurable Crossbar-Memory Hierarchy in 28nm.
VLSI Circuits
Sung Kim, Morteza Fayazi, Alhad Daftardar, Kuan-Yu Chen, Jielun Tan, Subhankar Pal, Tutu Ajayi, Yan Xiong, Trevor N. Mudge, Chaitali Chakrabarti, David T. Blaauw, Ronald G. Dreslinski, Hun-Seok Kim
2021 J jnl
Versa: A Dataflow-Centric Multiprocessor with 36 Systolic ARM Cortex-M4F Cores and a Reconfigurable Crossbar-Memory Hierarchy in 28nm.
CoRR
Sung Kim, Morteza Fayazi, Alhad Daftardar, Kuan-Yu Chen, Jielun Tan, Subhankar Pal, Tutu Ajayi, Yan Xiong, Trevor N. Mudge, Chaitali Chakrabarti, David T. Blaauw, Ronald G. Dreslinski, Hun-Seok Kim
2020 C conf
An Open-source Framework for Autonomous SoC Design with Analog Block Generation.
VLSI-SOC
Tutu Ajayi, Sumanth Kamineni, Yaswanth K. Cherivirala, Morteza Fayazi, Kyumin Kwon, Mehdi Saligane, Shourya Gupta, Chien-Hen Chen, Dennis Sylvester, David T. Blaauw, Ronald G. Dreslinski, Benton H. Calhoun, David D. Wentzloff
2020 — conf
Fully-Autonomous SoC Synthesis Using Customizable Cell-Based Analog and Mixed-Signal Circuits Generation.
VLSI-SoC (Selected Papers)
Tutu Ajayi, Sumanth Kamineni, Morteza Fayazi, Yaswanth K. Cherivirala, Kyumin Kwon, Shourya Gupta, Wenbo Duan, Jeongsup Lee, Chien-Hen Chen, Mehdi Saligane, Dennis Sylvester, David T. Blaauw, Ronald Dreslinski Jr., Benton H. Calhoun, David D. Wentzloff
2019 J jnl
A Simplified Approach to Two-Port Analysis in Feedback.
CoRR
Morteza Fayazi, Ali Fotowat, Zahra Kavehvash
2017 J jnl
Structural relations between brain-behavioral systems, social anxiety, depression and internet addiction: With regard to revised Reinforcement Sensitivity Theory (r-RST).
Comput. Hum. Behav.
Morteza Fayazi, Jafar Hasani