Moritoshi Yasunaga

74 papers A* 1A 3B 18C 3Journal 25Unranked 23

Year	Rank	Type	Title / Venue / Authors
2024	C	`conf`	A FPGA-based Learning Accelerator for Self-Organizing Map and Its Application to Trend-Visualization. ICCE Yusuke Yamagiwa, Kenji Kanazawa, Moritoshi Yasunaga
2024	J	`jnl`	A highly scalable Self-organizing Map accelerator on FPGA and its performance evaluation. Artif. Life Robotics Yusuke Yamagiwa, Yuki Kawahara, Kenji Kanazawa, Moritoshi Yasunaga
2024	C	`conf`	FPGA Implementation of Minimum Spanning Tree Calculation Towards Application for Capacitated Vehicle Routing Problems. ICCE Jiheng Wang, Kenji Kanazawa, Moritoshi Yasunaga
2019	—	`conf`	FPGA-Based Object Detection for Autonomous Driving System. FPT Kenichi Harada, Kenji Kanazawa, Moritoshi Yasunaga
2018	J	`jnl`	Evolutionary design of high signal integrity interconnection based on eye-diagram. Artif. Life Robotics Tetsuya Odaira, Naoki Yokoshima, Ikuo Yoshihara, Moritoshi Yasunaga
2016	C	`conf`	A passive equalizer and its design methodology for global interconnects in VLSIs. VLSI-SoC Moritoshi Yasunaga, Naoki Yokoshima, Ikuo Yoshihara
2016	J	`jnl`	An FPGA Solver for Partial MaxSAT Problems Based on Stochastic Local Search. SIGARCH Comput. Archit. News Shohei Sassa, Kenji Kanazawa, Shaowei Cai, Moritoshi Yasunaga
2016	J	`jnl`	An evolutionary design methodology of printed circuit boards for high-speed VLSIs. Artif. Life Robotics Moritoshi Yasunaga, Ikuo Yoshihara
2015	J	`jnl`	Foreword. IEICE Trans. Inf. Syst. Moritoshi Yasunaga
2015	—	`conf`	High-Speed Calculation of Convex Hull in 2D Images Using FPGA. PARCO Kenji Kanazawa, Kahori Kemmotsu, Yamato Mori, Noriyuki Aibe, Moritoshi Yasunaga
2015	—	`conf`	Simultaneous Improvement to Signal Integrity and Electromagnetic Interference in High-Speed Transmission Lines. SSCI Moritoshi Yasunaga, Yusuke Kuribara, Hirofumi Inoue, Ikuo Yoshihara
2014	—	`conf`	Segmental transmission line: Its practical application the optimized PCB trace design using a genetic algorithm. ICES Moritoshi Yasunaga, Hiroki Shimada, Katsuyuki Seki, Ikuo Yoshihara
2011	J	`jnl`	Digital-signal-waveform improvement on VLSI packaging including inductances. Artif. Life Robotics Hiroki Shimada, Shohei Akita, Masami Ishiguro, Noriyuki Aibe, Ikuo Yoshihara, Moritoshi Yasunaga
2010	B	`conf`	A proposal for Zoning Crossover of Hybrid Genetic Algorithms for large-scale traveling salesman problems. IEEE Congress on Evolutionary Computation Masafumi Kuroda, Kunihito Yamamori, Masaharu Munetomo, Moritoshi Yasunaga, Ikuo Yoshihara
2010	J	`jnl`	Development of a novel crossover of hybrid genetic algorithms for large-scale traveling salesman problems. Artif. Life Robotics Masafumi Kuroda, Kunihito Yamamori, Masaharu Munetomo, Moritoshi Yasunaga, Ikuo Yoshihara
2010	J	`jnl`	Signal-integrity improvement method and its robustness evaluation for VLSI and VLSI-packaging. Artif. Life Robotics Masami Ishiguro, Hiroshi Nakayama, Yuki Shimauchi, Noriyuki Aibe, Ikuo Yoshihara, Moritoshi Yasunaga
2009	J	`jnl`	A visual-inspection system using a self-organizing map. Artif. Life Robotics Keiko Ikeda, Moritoshi Yasunaga, Yoshiki Yamaguchi, Yorihisa Yamamoto, Ikuo Yoshihara
2008	J	`jnl`	A reconfigurable VLSI-based double-lens tracking camera. Artif. Life Robotics Moritoshi Yasunaga, Noriyuki Aibe, Yoshiki Yamaguchi, Yorihisa Yamamoto, Takaaki Awano, Ikuo Yoshihara
2008	—	`conf`	An adaptive pattern recognition hardware with on-chip shift register-based partial reconfiguration. FPT Hiroyuki Kawai, Yoshiki Yamaguchi, Moritoshi Yasunaga, Kyrre Glette, Jim Tørresen
2008	J	`jnl`	Real-world applications on the reconfigurable-VLSI-based double-lens tracking-camera. Artif. Life Robotics Moritoshi Yasunaga, Noriyuki Aibe, Yoshiki Yamaguchi, Yorihisa Yamamoto, Takaaki Awano, Ikuo Yoshihara
2008	—	`conf`	The Segmental-Transmission-Line: Its Design and Prototype Evaluation. ICES Moritoshi Yasunaga, Yoshiki Yamaguchi, Hiroshi Nakayama, Ikuo Yoshihara, Naoki Koizumi, Jung Hwan Kim
2008	J	`jnl`	Variable-length segmental transmission line and its design guidelines. Artif. Life Robotics Naoki Koizumi, Kazuya Hayashi, Moritoshi Yasunaga, Kunihito Yamamori, Ikuo Yoshihara
2007	—	`conf`	A Lattice Gas Cellular Automata Simulator on the Cell Broadband Engine. PARCO Yusuke Arai, Ryo Sawai, Yoshiki Yamaguchi, Tsutomu Maruyama, Moritoshi Yasunaga
2007	J	`jnl`	A New Three-Level Tree Data Structure for Representing TSP Tours in the Lin-Kernighan Heuristic. IEICE Trans. Fundam. Electron. Commun. Comput. Sci. Hung Dinh Nguyen, Ikuo Yoshihara, Kunihito Yamamori, Moritoshi Yasunaga
2007	J	`jnl`	A bio-inspired tracking camera system. Artif. Life Robotics Yoshiki Yamaguchi, Moritoshi Yasunaga, Kazuya Hayashi, Noriyuki Aibe, Yorihisa Yamamoto, Ikuo Yoshihara
2007	—	`conf`	An Online EHW Pattern Recognition System Applied to Face Image Recognition. EvoWorkshops Kyrre Glette, Jim Tørresen, Moritoshi Yasunaga
2007	—	`conf`	An Online EHW Pattern Recognition System Applied to Sonar Spectrum Classification. ICES Kyrre Glette, Jim Tørresen, Moritoshi Yasunaga
2007	—	`conf`	Bio-Inspired Functional Asymmetry Camera System. ICONIP (2) Yoshiki Yamaguchi, Noriyuki Aibe, Moritoshi Yasunaga, Yorihisa Yamamoto, Takaaki Awano, Ikuo Yoshihara
2007	J	`jnl`	Implementation of an Effective Hybrid GA for Large-Scale Traveling Salesman Problems. IEEE Trans. Syst. Man Cybern. Part B Hung Dinh Nguyen, Ikuo Yoshihara, Kunihito Yamamori, Moritoshi Yasunaga
2007	J	`jnl`	Mesoscopic-level Simulation of Dynamics and Interactions of Biological Molecules Using Monte Carlo Simulation. J. VLSI Signal Process. Yoshiki Yamaguchi, Tsutomu Maruyama, Ryuzo Azuma, Moritoshi Yasunaga, Akihiko Konagaya
2007	—	`conf`	Online Evolution for a High-Speed Image Recognition System Implemented On a Virtex-II Pro FPGA. AHS Kyrre Glette, Jim Tørresen, Moritoshi Yasunaga
2006	B	`conf`	Enhancement of the Variable-Length-Transmission-Line design method for multi-point optimization. IEEE Congress on Evolutionary Computation Naoki Koizumi, Ikuo Yoshihara, Kunihito Yamamori, Moritoshi Yasunaga
2006	—	`conf`	On-Chip Evolution Using a Soft Processor Core Applied to Image Recognition. AHS Kyrre Glette, Jim Tørresen, Moritoshi Yasunaga, Yoshiki Yamaguchi
2006	—	`conf`	Realization of the sound space environment for the radiation-tolerant space craft. ReConFig Hiroyuki Kawai, Yoshiki Yamaguchi, Moritoshi Yasunaga
2005	B	`conf`	Finding transcriptional regulatory elements in Dictyostelium gene expression. Congress on Evolutionary Computation Daekwan Seo, Moritoshi Yasunaga, Insook Kim, Byungwoon Ham, Jung Hwan Kim
2005	B	`conf`	Variable length segmental-transmission-line and its parameter optimization based on GA. Congress on Evolutionary Computation Naoki Koizumi, Ikuo Yoshihara, Kunihito Yamamori, Moritoshi Yasunaga
2004	B	`conf`	A computational approach to detect regulatory elements in Dictyostelium discoideum. IEEE Congress on Evolutionary Computation Daekwan Seo, Moritoshi Yasunaga, Jung Hwan Kim
2004	J	`jnl`	A multimodal neural network with single-state predictions for protein secondary structure. Artif. Life Robotics Hanxi Zhu, Ikuo Yoshihara, Kunihito Yamamori, Moritoshi Yasunaga
2004	J	`jnl`	A multimodal neural network with single-state predictions for protein secondary structure. Artif. Life Robotics Hanxi Zhu, Ikuo Yoshihara, Kunihito Yamamori, Moritoshi Yasunaga
2004	J	`jnl`	Multi-Modal Neural Networks for Symbolic Sequence Pattern Classification. IEICE Trans. Inf. Syst. Hanxi Zhu, Ikuo Yoshihara, Kunihito Yamamori, Moritoshi Yasunaga
2004	J	`jnl`	Performance evaluation system for probabilistic neural network hardware. Artif. Life Robotics Noriyuki Aibe, Ryosuke Mizuno, Masanori Nakamura, Moritoshi Yasunaga, Ikuo Yoshihara
2004	J	`jnl`	Performance evaluation system for probabilistic neural network hardware. Artif. Life Robotics Noriyuki Aibe, Ryosuke Mizuno, Masanori Nakamura, Moritoshi Yasunaga, Ikuo Yoshihara
2004	—	`conf`	Reconfigurable I/O interface for mobile equipments. FPT Noriyuki Aibe, Moritoshi Yasunaga
2003	—	`conf`	Gene Finding Using Evolvable Reasoning Hardware. ICES Moritoshi Yasunaga, Ikuo Yoshihara, Jung Hwan Kim
2003	B	`conf`	Improved GA-based method for multiple protein sequence alignment. IEEE Congress on Evolutionary Computation Hung Dinh Nguyen, Kunihito Yamamori, Ikuo Yoshihara, Moritoshi Yasunaga
2003	—	`conf`	Reconfigurable architecture for probabilistic neural network system. FPT Ryosuke Mizuno, Noriyuki Aibe, Moritoshi Yasunaga, Ikuo Yoshihara
2003	—	`conf`	Reconfigurable parallel comparation architecture and its application to IP packet filters. FPT Noriyuki Aibe, Moritoshi Yasunaga
2003	B	`conf`	The design of segmental-transmission-line for high-speed digital signals using genetic algorithms. IEEE Congress on Evolutionary Computation Moritoshi Yasunaga, Ikuo Yoshihara, Jung Hwan Kim
2002	B	`conf`	A parallel hybrid genetic algorithm for multiple protein sequence alignment. IEEE Congress on Evolutionary Computation Hung Dinh Nguyen, Ikuo Yoshihara, Kunihito Yamamori, Moritoshi Yasunaga
2002	B	`conf`	An evolutionary kernel-based reasoning system using reconfigurable VLSIs: its hardware prototyping and application to the splicing boundary problem. IEEE Congress on Evolutionary Computation Moritoshi Yasunaga, Kentaro Ushiyama, Noriyuki Aibe, Hidetoshi Fujiwara, Ikuo Yoshiyara, Jung H. Kim
2002	—	`conf`	Prediction of protein secondary Structure by Multi-Modal Neural Networks. SEAL Hanxi Zhu, Ikuo Yoshihara, Kunihito Yamamori, Moritoshi Yasunaga
2001	J	`jnl`	Evolvable Reasoning Hardware: Its Prototyping and Performance Evaluation. Genet. Program. Evolvable Mach. Moritoshi Yasunaga, Jung Hwan Kim, Ikuo Yoshihara
2001	—	`ed.`	Evolvable Systems: From Biology to Hardware, 4th International Conference, ICES 2001 Tokyo, Japan, October 3-5, 2001, Proceedings ICES Yong Liu, Kiyoshi Tanaka, Masaya Iwata, Tetsuya Higuchi, Moritoshi Yasunaga
2001	B	`conf`	Evolvable reasoning hardware: its application to the genome informatics. CEC Moritoshi Yasunaga, Takahiro Tsuzuku, Kentaro Ushiyama, Ikuo Yoshihara, Jung H. Kim
2001	J	`jnl`	Robust noncoherent PN-code acquisition for CDMA communication systems. IEEE Trans. Veh. Technol. Jung Hwan Kim, Shanuj V. Sarin, Moritoshi Yasunaga, Hyunseo Oh
2000	A	`conf`	A Fast Model-Building Method for Time Series Using Genetic Programming. GECCO Ikuo Yoshihara, Tomoo Aoyama, Moritoshi Yasunaga
2000	—	`conf`	A High Speed and High Fault Tolerant Reconfigurable Reasoning System: Toward a Wafer Scale Reconfigurable Reasoning LSI. DFT Moritoshi Yasunaga, Ikuo Yoshihara, Jung Hwan Kim
2000	B	`conf`	GA-based kernel optimization for pattern recognition: theory for EHW application. CEC Moritoshi Yasunaga, Taro Nakamura, Ikuo Yoshihara, Jung H. Kim
2000	B	`conf`	GP-based modeling method for time series prediction with parameter optimization and node alternation. CEC Ikuo Yoshihara, Tomoo Aoyama, Moritoshi Yasunaga
2000	—	`conf`	Genetic Algorithm-Based Methodology for Pattern Recognition Hardware. ICES Moritoshi Yasunaga, Taro Nakamura, Ikuo Yoshihara, Jung Hwan Kim
2000	A	`conf`	Kernel Optimization in Pattern Recognition Using a Genetic Algorithm. GECCO Moritoshi Yasunaga, Taro Nakamura, Ikuo Yoshihara, Jung Hwan Kim
2000	—	`conf`	Kernel-Based Pattern Recognition Hardware: Its Design Methodology Using Evolved Truth Tables. Evolvable Hardware Moritoshi Yasunaga, Taro Nakamura, Jung Hwan Kim, Ikuo Yoshihara
2000	A	`conf`	The application of genetic algorithms to the design of reconfigurable reasoning VLSI chips. FPGA Moritoshi Yasunaga, Jung Hwan Kim, Ikuo Yoshihara
1999	B	`conf`	A multi-modal neural network using Chebyschev polynomials and its application. IJCNN Ikuo Yoshihara, Tomoyuki Nakagawa, Moritoshi Yasunaga, Kenichi Abe
1999	B	`conf`	Parallel back-propagation using genetic algorithm: real-time BP learning on the massively parallel computer CP-PACS. IJCNN Moritoshi Yasunaga, Eiji Yoshida, Ikuo Yoshihara
1999	B	`conf`	Parallel self-organization map using multiple stimuli. IJCNN Moritoshi Yasunaga, Kenichi Tominaga, Jung Hwan Kim
1999	B	`conf`	Sonar spectrum recognition chip designed by evolutionary algorithm. IJCNN Moritoshi Yasunaga, Taro Nakamura, Ikuo Yoshihara
1998	B	`conf`	Dynamic Optical Topography and the Real-Time PDP Chip: An Analytical and Synthetical Approach to Higher-Order Brain Functions. ICONIP Hirokazu Koizumi, T. Ochiai, T. Okahashi, Yuichi Yamashita, Atsushi Maki, T. Yamamoto, Y. Inagami, H. Yoshizawa, Masaya Iwata, Takashi Omori, Moritoshi Yasunaga
1998	J	`jnl`	Fault-tolerant self-organizing map implemented by wafer-scale integration. IEEE Trans. Very Large Scale Integr. Syst. Moritoshi Yasunaga, I. Hachiya, K. Moki, Jung Hwan Kim
1998	—	`conf`	Performance of a bus-based parallel computer with integer-representation processors applied to artificial neural network and parallel AI domains. KES (3) Moritoshi Yasunaga, Akio Yamada, T. Okahashi
1997	—	`conf`	Ising model calculation using PDM neural network hardware: Boltzmann statistical mechanics embedded in the hardware. ICNN Moritoshi Yasunaga, Yuzo Hirai
1993	J	`jnl`	A self-learning digital neural network using wafer-scale LSI. IEEE J. Solid State Circuits Moritoshi Yasunaga, Noboru Masuda, Masayoshi Yagyu, Mitsuo Asai, Katsunari Shibata, Mitsuo Ooyama, Minoru Yamada, Takahiro Sakaguchi, Masashi Hashimoto
1992	A*	`conf`	Wafer Scale Integration for Massively Parallel Memory-Based Reasoning. AAAI Hiroaki Kitano, Moritoshi Yasunaga
1990	B	`conf`	Design, fabrication and evaluation of a 5-inch wafer scale neural network LSI composed on 576 digital neurons. IJCNN Moritoshi Yasunaga, Noboru Masuda, Masayoshi Yagyu, Mitsuo Asai, Minoru Yamada, Akira Masaki