Morihiro Kuga - RankMe

47 papers A* 1A 1B 6C 4Misc 2Journal 16Unranked 17

Year	Rank	Type	Title / Venue / Authors
2024	J	`jnl`	Applying Run-Length Compression to the Configuration Data of SLM Fine-Grained Reconfigurable Logic. IEICE Trans. Inf. Syst. Souhei Takagi, Takuya Kojima, Hideharu Amano, Morihiro Kuga, Masahiro Iida
2024	—	`conf`	SLMLET: A RISC-V Processor SoC with Tightly-Coupled Area-Efficient eFPGA Blocks. COOL CHIPS Takuya Kojima, Yosuke Yanai, Hayate Okuhara, Hideharu Amano, Morihiro Kuga, Masahiro Iida
2023	J	`jnl`	An eFPGA Generation Suite with Customizable Architecture and IDE. IEICE Trans. Fundam. Electron. Commun. Comput. Sci. Morihiro Kuga, Qian Zhao, Yuya Nakazato, Motoki Amagasaki, Masahiro Iida
2022	B	`conf`	FPL Demo: An FPGA-IP Prototype Chip for MEC devices. FPL Morihiro Kuga, Masahiro Iida, Hideharu Amano
2021	—	`conf`	Automation of Domain-specific FPGA-IP Generation and Test. HEART Yuya Nakazato, Motoki Amagasaki, Qian Zhao, Masahiro Iida, Morihiro Kuga
2018	J	`jnl`	Enabling FPGA-as-a-Service in the Cloud with hCODE Platform. IEICE Trans. Inf. Syst. Qian Zhao, Motoki Amagasaki, Masahiro Iida, Morihiro Kuga, Toshinori Sueyoshi
2017	—	`conf`	FPGA based ASIC Emulator with High Speed Optical Serial Links. HEART Motoki Amagasaki, Futoshi Murase, Morihiro Kuga, Masahiro Iida, Toshinori Sueyoshi
2017	—	`conf`	High-level Synthesis based on Parallel Design Patterns using a Functional Language. HEART Morihiro Kuga, Kansuke Fukuda, Motoki Amagasaki, Masahiro Iida, Toshinori Sueyoshi
2017	J	`jnl`	Physical Fault Detection and Recovery Methods for System-LSI Loaded FPGA-IP Core. IEICE Trans. Inf. Syst. Motoki Amagasaki, Yuki Nishitani, Kazuki Inoue, Masahiro Iida, Morihiro Kuga, Toshinori Sueyoshi
2017	J	`jnl`	Towards Open-HW: A Platform to Design, Share and Deploy FPGA Accelerators in Low Cost. IPSJ Trans. Syst. LSI Des. Methodol. Qian Zhao, Motoki Amagasaki, Masahiro Iida, Morihiro Kuga, Toshinori Sueyoshi
2017	—	`conf`	hCODE 2.0: An open-source toolkit for building efficient FPGA-enabled clouds. FPT Qian Zhao, Hendarmawan, Motoki Amagasaki, Masahiro Iida, Morihiro Kuga, Toshinori Sueyoshi
2016	J	`jnl`	A Study of Heterogeneous Computing Design Method based on Virtualization Technology. SIGARCH Comput. Archit. News Qian Zhao, Motoki Amagasaki, Masahiro Iida, Morihiro Kuga, Toshinori Sueyoshi
2016	—	`conf`	hCODE: An open-source platform for FPGA accelerators. FPT Qian Zhao, Takuya Nakamichi, Motoki Amagasaki, Masahiro Iida, Morihiro Kuga, Toshinori Sueyoshi
2015	J	`jnl`	A 3D FPGA Architecture to Realize Simple Die Stacking. Inf. Media Technol. Motoki Amagasaki, Qian Zhao, Masahiro Iida, Morihiro Kuga, Toshinori Sueyoshi
2015	J	`jnl`	A 3D FPGA Architecture to Realize Simple Die Stacking. IPSJ Trans. Syst. LSI Des. Methodol. Motoki Amagasaki, Qian Zhao, Masahiro Iida, Morihiro Kuga, Toshinori Sueyoshi
2015	C	`conf`	Architecture exploration of 3D FPGA to minimize internal layer connection. VLSI-SoC Motoki Amagasaki, Yuto Takeuchi, Qian Zhao, Masahiro Iida, Morihiro Kuga, Toshinori Sueyoshi
2015	J	`jnl`	Fault-Tolerant FPGA: Architectures and Design for Programmable Logic Intellectual Property Core in SoC. IEICE Trans. Inf. Syst. Motoki Amagasaki, Qian Zhao, Masahiro Iida, Morihiro Kuga, Toshinori Sueyoshi
2015	—	`conf`	Simple wafer stacking 3D-FPGA architecture. ICICDT Motoki Amagasaki, Qian Zhao, Masahiro Iida, Morihiro Kuga, Toshinori Sueyoshi
2014	B	`conf`	A logic cell architecture exploiting the shannon expansion for the reduction of configuration memory. FPL Qian Zhao, Kyosei Yanagida, Motoki Amagasaki, Masahiro Iida, Morihiro Kuga, Toshinori Sueyoshi
2014	—	`conf`	Blokus Duo engine on a Zynq. FPT Susumu Mashimo, Kansuke Fukuda, Motoki Amagasaki, Masahiro Iida, Morihiro Kuga, Toshinori Sueyoshi
2014	—	`conf`	Zyndroid: An Android platform for software/hardware coprocessing. FPT Susumu Mashimo, Motoki Amagasaki, Masahiro Iida, Morihiro Kuga, Toshinori Sueyoshi
2013	A	`conf`	A novel FPGA design framework with VLSI post-routing performance analysis (abstract only). FPGA Qian Zhao, Kazuki Inoue, Motoki Amagasaki, Masahiro Iida, Morihiro Kuga, Toshinori Sueyoshi
2013	J	`jnl`	A reconfigurable Java accelerator with software compatibility for embedded systems. SIGARCH Comput. Archit. News Yuki Ogawa, Masahiro Iida, Motoki Amagasaki, Morihiro Kuga, Toshinori Sueyoshi
2013	—	`conf`	An FPGA design and implementation framework combined with commercial VLSI CADs. ReCoSoC Qian Zhao, Motoki Amagasaki, Masahiro Iida, Morihiro Kuga, Toshinori Sueyoshi
2013	B	`conf`	An automatic FPGA design and implementation framework. FPL Qian Zhao, Motoki Amagasaki, Masahiro Iida, Morihiro Kuga, Toshinori Sueyoshi
2013	B	`conf`	Defect-robust FPGA architectures for intellectual property cores in system LSI. FPL Motoki Amagasaki, Kazuki Inoue, Qian Zhao, Masahiro Iida, Morihiro Kuga, Toshinori Sueyoshi
2013	J	`jnl`	FPGA Design Framework Combined with Commercial VLSI CAD. IEICE Trans. Inf. Syst. Qian Zhao, Kazuki Inoue, Motoki Amagasaki, Masahiro Iida, Morihiro Kuga, Toshinori Sueyoshi
2013	C	`conf`	Three-dimensional stacking FPGA architecture using face-to-face integration. VLSI-SoC Tetsuro Hamada, Qian Zhao, Motoki Amagasaki, Masahiro Iida, Morihiro Kuga, Toshinori Sueyoshi
2012	—	`conf`	A Bitstream Relocation Technique to Improve Flexibility of Partial Reconfiguration. ICA3PP (1) Yoshihiro Ichinomiya, Motoki Amagasaki, Masahiro Iida, Morihiro Kuga, Toshinori Sueyoshi
2012	—	`conf`	A novel physical defects recovery technique for FPGA-IP cores. ReConFig Yuki Nishitani, Kazuki Inoue, Motoki Amagasaki, Masahiro Iida, Morihiro Kuga, Toshinori Sueyoshi
2012	—	`conf`	Accelerated evaluation of SEU failure-in-time using frame-based partial reconfiguration. FPT Yoshihiro Ichinomiya, Kohei Takano, Motoki Amagasaki, Morihiro Kuga, Masahiro Iida, Toshinori Sueyoshi
2012	Misc	`conf`	Designing Flexible Reconfigurable Regions to Relocate Partial Bitstreams. FCCM Yoshihiro Ichinomiya, Sadaki Usagawa, Motoki Amagasaki, Masahiro Iida, Morihiro Kuga, Toshinori Sueyoshi
2012	C	`conf`	Evaluation of fault tolerant technique based on homogeneous FPGA architecture. VLSI-SoC Yuki Nishitani, Kazuki Inoue, Motoki Amagasaki, Masahiro Iida, Morihiro Kuga, Toshinori Sueyoshi
2012	—	`conf`	Fault Recovery Technique for TMR Softcore Processor System Using Partial Reconfiguration. ICA3PP (1) Makoto Fujino, Hiroki Tanaka, Yoshihiro Ichinomiya, Motoki Amagasaki, Morihiro Kuga, Masahiro Iida, Toshinori Sueyoshi
2012	B	`conf`	Fault detection and avoidance of FPGA in various granularities. FPL Kazuki Inoue, Yuki Nishitani, Motoki Amagasaki, Masahiro Iida, Morihiro Kuga, Toshinori Sueyoshi
2012	J	`jnl`	Fault-Injection Analysis to Estimate SEU Failure in Time by Using Frame-Based Partial Reconfiguration. IEICE Trans. Fundam. Electron. Commun. Comput. Sci. Yoshihiro Ichinomiya, Tsuyoshi Kimura, Motoki Amagasaki, Morihiro Kuga, Masahiro Iida, Toshinori Sueyoshi
2011	J	`jnl`	Improving the Soft-error Tolerability of a Soft-core Processor on. J. Next Gener. Inf. Technol. Yoshihiro Ichinomiya, Motoki Amagasaki, Masahiro Iida, Morihiro Kuga, Toshinori Sueyoshi
2011	J	`jnl`	Parallelization of the channel width search for FPGA routing. SIGARCH Comput. Archit. News Hiroomi Sawada, Morihiro Kuga, Motoki Amagasaki, Masahiro Iida, Toshinori Sueyoshi
2010	Misc	`conf`	Improving the Robustness of a Softcore Processor against SEUs by Using TMR and Partial Reconfiguration. FCCM Yoshihiro Ichinomiya, Shiro Tanoue, Motoki Amagasaki, Masahiro Iida, Morihiro Kuga, Toshinori Sueyoshi
2010	C	`conf`	Power-aware FPGA routing fabrics and design tools. VLSI-SoC Shoichi Nishida, Jyunya Eto, Motoki Amagasaki, Masahiro Iida, Morihiro Kuga, Toshinori Sueyoshi
2009	B	`conf`	A novel states recovery technique for the TMR softcore processor. FPL Shiro Tanoue, Tomoyuki Ishida, Yoshihiro Ichinomiya, Motoki Amagasaki, Morihiro Kuga, Toshinori Sueyoshi
2009	—	`conf`	Memory Sharing Approach for TMR Softcore Processor. ARC Yoshihiro Ichinomiya, Shiro Tanoue, Tomoyuki Ishida, Motoki Amagasaki, Morihiro Kuga, Toshinori Sueyoshi
2004	—	`conf`	EXPRESS-1: a dynamically reconfigurable platform using embedded processor FPGA. FPT Hidetomo Shibamura, Masayuki Fukuyama, Daisuke Uchida, Seiji Ikeda, Morihiro Kuga, Toshinori Sueyoshi
2002	J	`jnl`	KITE microprocessor and CAE for computer science. Syst. Comput. Jpn. Toshinori Sueyoshi, Morihiro Kuga, Hidetomo Shibamura
1994	—	`conf`	Overview of the JUMP-1, an MPP prototype for general-purpose parallel computations. ISPAN Kei Hiraki, Hideharu Amano, Morihiro Kuga, Toshinori Sueyoshi, Tomohiro Kudoh, Hiroshi Nakashima, Hironori Nakajo, Hideo Matsuda, Takashi Matsumoto, Shin-ichiro Mori
1991	J	`jnl`	DSNS (dynamically-hazard-resolved statically-code-scheduled, nonuniform superscalar): yet another superscalar processor architecture. SIGARCH Comput. Archit. News Morihiro Kuga, Kazuaki J. Murakami, Shinji Tomita
1989	A*	`conf`	SIMP (Single Instruction stream/Multiple Instruction Pipelining): A Novel High-Speed Single-Processor Architecture. ISCA Kazuaki J. Murakami, Naohiko Irie, Morihiro Kuga, Shinji Tomita