Moon-Chul Choi

12 papers Journal 6Unranked 6
YearRankTypeTitle / Venue / Authors
2025 — conf
30.3 A 24Gb 42.5Gb/s GDDR7 DRAM with Low-Power WCK Distribution, an RC-Optimized Dual-Emphasis TX, and Voltage/Time-Margin-Enhanced Power Reduction.
ISSCC
Sang-Hoon Kim, Jaehyeok Baek, Moon-Chul Choi, Daewoong Lee, Donggun An, Se-Mi Kim, Yeonggeun Song, Minkyo Shim, Sung-Yong Cho, Dongha Lee, Gun-hee Cho, Inwoo Jun, Juseop Park, Taeyoon Lee, Hwan-Chul Jung, Chanyong Lee, Gil-Young Kang, Hye-Ran Kim, Jongmyung Lee, Young Su Joo, Hyo-jin Jung, Bokyeon Won, Ji-Hak Yu, Sangkeun Han, Yechan Hwang, Chungman Kim, Seok-Jung Kim, Youngseok Lee, Young-Tae Kim, Myeong-O. Kim, Wonhwa Shin, Tae-Young Oh, Sangjoon Hwang
2025 J jnl
A 16-Gb 37-Gb/s GDDR7 DRAM With PAM3-Optimized TRX Equalization and ZQ Calibration.
IEEE J. Solid State Circuits
Sung-Yong Cho, Moon-Chul Choi, Jaehyeok Baek, Donggun An, Sang-Hoon Kim, Daewoong Lee, Seongyeal Yang, Se-Mi Kim, Gil-Young Kang, Juseop Park, Kyung-Ho Lee, Hwan-Chul Jung, Gun-hee Cho, Chan-Yong Lee, Hye-Ran Kim, Yong-Jae Shin, Hanna Park, Sang-Yong Lee, Jonghyuk Kim, Bokyeon Won, Jungil Mok, Kijin Kim, Unhak Lim, Hongjun Jin, Youngseok Lee, Young-Tae Kim, Heonjoo Ha, Jinchan Ahn, Wonju Sung, Yoontaek Jang, Hoyoung Song, Hyodong Ban, Taehoon Park, Changsik Yoo, Tae-Young Oh, Sangjoon Hwang
2024 — conf
13.6 A 16Gb 37Gb/s GDDR7 DRAM with PAM3-Optimized TRX Equalization and ZQ Calibration.
ISSCC
Sung-Yong Cho, Moon-Chul Choi, Jaehyeok Baek, Donggun An, Sanghoon Kim, Daewoong Lee, Seongyeal Yang, Gil-Young Kang, Juseop Park, Kyungho Lee, Hwan-Chul Jung, Gun-hee Cho, Chanyong Lee, Hye-Ran Kim, Yong-Jae Shin, Hanna Park, Sangyong Lee, Jonghyuk Kim, Bokyeon Won, Jungil Mok, Kijin Kim, Unhak Lim, Hongjun Jin, Youngseok Lee, Young-Tae Kim, Heonjoo Ha, Jinchan Ahn, Wonju Sung, Yoontaek Jang, Hoyoung Song, Hyodong Ban, Taehoon Park, Tae-Young Oh, Changsik Yoo, Sangjoon Hwang
2022 J jnl
A 2.5-32 Gb/s Gen 5-PCIe Receiver With Multi-Rate CDR Engine and Hybrid DFE.
IEEE Trans. Circuits Syst. II Express Briefs
Moon-Chul Choi, Sanghee Lee, Seungha Roh, Kwangho Lee, Jonghyun Oh, Sungwoo Kim, Kwandong Kim, Woo-Seok Choi, Jaeha Kim, Deog-Kyoon Jeong
2022 J jnl
A 64-Gb/s PAM-4 Receiver With Transition-Weighted Phase Detector.
IEEE Trans. Circuits Syst. II Express Briefs
Seungha Roh, Kwangho Lee, Minkyo Shim, Moon-Chul Choi, Deog-Kyoon Jeong
2021 J jnl
A 10 Gb/s PAM-4 Transmitter With Feed-Forward Implementation of Tomlinson-Harashima Precoding in 28 nm CMOS.
IEEE Access
Byungjun Kang, Gyu-Seob Jeong, Jeongho Hwang, Kwanseo Park, Hyungrok Do, Hyojun Kim, Han-Gon Ko, Moon-Chul Choi, Deog-Kyoon Jeong
2021 — conf
A Maximum Eye Tracking Clock-and-Data Recovery Scheme with Golden Section Search(GSS) Algorithm in 28-nm CMOS.
ISOCC
Seungha Roh, Moon-Chul Choi, Deog-Kyoon Jeong
2020 — conf
A 0.1-pJ/b/dB 28-Gb/s Maximum-Eye Tracking, Weight-Adjusting MM CDR and Adaptive DFE with Single Shared Error Sampler.
VLSI Circuits
Moon-Chul Choi, Han-Gon Ko, Jonghyun Oh, Hye-Yoon Joo, Kwangho Lee, Deog-Kyoon Jeong
2019 J jnl
A 2.5-28 Gb/s Multi-Standard Transmitter With Two-Step Time-Multiplexing Driver.
IEEE Trans. Circuits Syst. II Express Briefs
Moon-Chul Choi, Deog-Kyoon Jeong, Sung-Yong Cho, Minkyo Shim, Byungmin Kim, Han-Gon Ko, Haram Ju, Kwanseo Park, Hyojun Kim, Kwandong Kim
2019 — conf
A Design of Data Path Based on CMOS Logic for a 72-Gb/s PAM-4 Transmitter in 28-nm CMOS.
ICEIC
Moon-Chul Choi, Haram Ju, Han-Gon Ko, Deog-Kyoon Jeong
2018 — conf
A 64 GB/s 1.5 PJ/Bit PAM-4 Transmitter with 3-Tap FFE and GM-Regulated Active-Feedback Driver in 28 NM CMOS.
VLSI Circuits
Haram Ju, Moon-Chul Choi, Gyu-Seob Jeong, Deog-Kyoon Jeong
2017 J jnl
A 28 Gb/s 1.6 pJ/b PAM-4 Transmitter Using Fractionally Spaced 3-Tap FFE and G
IEEE Trans. Circuits Syst. II Express Briefs
Haram Ju, Moon-Chul Choi, Gyu-Seob Jeong, Woo-Rham Bae, Deog-Kyoon Jeong