Monodeep Kar - RankMe

52 papers A* 1A 8B 1C 1Journal 17Unranked 23

Year	Rank	Type	Title / Venue / Authors
2026	J	`jnl`	Is Finer Better? The Limits of Microscaling Formats in Large Language Models. CoRR Andrea Fasoli, Monodeep Kar, Chi-Chun (Charlie) Liu, Swagath Venkataramani, Viji Srinivasan, Leland Chang, Naigang Wang
2026	—	`conf`	Spyre: An Inference-Optimized Scalable AI Accelerator for Enterprise Workloads. ISSCC Matthew Cohen, Monodeep Kar, Swagath Venkataramani, Viji Srinivasan, Brian Veraa, Matthew M. Ziegler, Nianzheng Cao, Ashish Ranjan, Joel Silberman, Michael Guillorn, Sandra Woodward, JohnDavid Lancaster, Josh Hursey, Kyu-Hyoun Kim, Alberto Mannari, Amrit Nagarajan, Ananda Samajdar, Bahman Hekmatshoartabari, Bob Galbraith, Ching Zhou, David L. Satterfield, Gregory S. Still, Gustavo Tellez, Indira Nair, Indu Masilamanai, Jinwook Jung, Kavi Randhawa, Marcel Schaal, Martin Lutz, Paul Crumley, Philip Jacob, Prasanth Chatarasi, Radhika Jain, Sae Kyu Lee, Sanchari Sen, Sarada Krithivasan, Scot Rider, Shubham Jain, Siyu Koswatta, Thomas Roewer, Tom Gooding, Victor Ferrari, Vidhi Zalani, Zhibin Ren, Kevin Reick, Lisa Maurice, Christopher J. Gonzalez, Chris Catalino, Ryan Nett, Pong-Fei Lu, Robert M. Senger, Leland Chang
2025	J	`jnl`	Power-Limited Inference Performance Optimization Using a Software-Assisted Peak Current Regulation Scheme in a 5-nm AI SoC. IEEE J. Solid State Circuits Monodeep Kar, Joel Silberman, Swagath Venkataramani, Viji Srinivasan, Bruce M. Fleischer, Joshua Rubin, JohnDavid Lancaster, Sae Kyu Lee, Matthew Cohen, Matthew M. Ziegler, Nianzheng Cao, Sandra Woodward, Ankur Agrawal, Ching Zhou, Prasanth Chatarasi, Thomas Gooding, Michael Guillorn, Bahman Hekmatshoartabari, Philip Jacob, Radhika Jain, Shubham Jain, Jinwook Jung, Kyu-Hyoun Kim, Siyu Koswatta, Martin Lutz, Alberto Mannari, Abey Mathew, Indira Nair, Ashish Ranjan, Zhibin Ren, Scot Rider, Thomas Röwer, David L. Satterfield, Marcel Schaal, Sanchari Sen, Gustavo Tellez, Hung Tran, Wei Wang, Vidhi Zalani, Jintao Zhang, Xin Zhang, Vinay Shah, Robert M. Senger, Arvind Kumar, Pong-Fei Lu, Leland Chang
2024	—	`conf`	14.1 A Software-Assisted Peak Current Regulation Scheme to Improve Power-Limited Inference Performance in a 5nm AI SoC. ISSCC Monodeep Kar, Joel Silberman, Swagath Venkataramani, Viji Srinivasan, Bruce M. Fleischer, Joshua Rubin, JohnDavid Lancaster, Sae Kyu Lee, Matthew Cohen, Matthew M. Ziegler, Nianzheng Cao, Sandra Woodward, Ankur Agrawal, Ching Zhou, Prasanth Chatarasi, Thomas Gooding, Michael Guillorn, Bahman Hekmatshoartabari, Philip Jacob, Radhika Jain, Shubham Jain, Jinwook Jung, Kyu-Hyoun Kim, Siyu Koswatta, Martin Lutz, Alberto Mannari, Abey Mathew, Indira Nair, Ashish Ranjan, Zhibin Ren, Scot Rider, Thomas Roewer, David L. Satterfield, Marcel Schaal, Sanchari Sen, Gustavo Tellez, Hung Tran, Wei Wang, Vidhi Zalani, Jintao Zhang, Xin Zhang, Vinay Shah, Robert M. Senger, Arvind Kumar, Pong-Fei Lu, Leland Chang
2023	—	`conf`	A Switched-Capacitor Integer Compute Unit with Decoupled Storage and Arithmetic for Cloud AI Inference in 5nm CMOS. VLSI Technology and Circuits Ankur Agrawal, Monodeep Kar, Kyu-Hyoun Kim, Sergey V. Rylov, Jinwook Jung, Seiji Munetoh, Kohji Hosokawa, Xin Zhang, Bahman Hekmatshoartabari, Fabio Carta, Martin Cochet, Robert Casatuta, Mingu Kang, Sunil Shukla, Kailash Gopalakrishnan, Leland Chang
2022	J	`jnl`	A 7-nm Four-Core Mixed-Precision AI Chip With 26.2-TFLOPS Hybrid-FP8 Training, 104.9-TOPS INT4 Inference, and Workload-Aware Throttling. IEEE J. Solid State Circuits Sae Kyu Lee, Ankur Agrawal, Joel Silberman, Matthew M. Ziegler, Mingu Kang, Swagath Venkataramani, Nianzheng Cao, Bruce M. Fleischer, Michael Guillorn, Matthew Cohen, Silvia M. Mueller, Jinwook Oh, Martin Lutz, Jinwook Jung, Siyu Koswatta, Ching Zhou, Vidhi Zalani, Monodeep Kar, James Bonanno, Robert Casatuta, Chia-Yu Chen, Jungwook Choi, Howard Haynie, Alyssa Herbert, Radhika Jain, Kyu-Hyoun Kim, Yulong Li, Zhibin Ren, Scot Rider, Marcel Schaal, Kerstin Schelm, Michael Scheuermann, Xiao Sun, Hung Tran, Naigang Wang, Wei Wang, Xin Zhang, Vinay Shah, Brian W. Curran, Vijayalakshmi Srinivasan, Pong-Fei Lu, Sunil Shukla, Kailash Gopalakrishnan, Leland Chang
2021	J	`jnl`	A 617-TOPS/W All-Digital Binary Neural Network Accelerator in 10-nm FinFET CMOS. IEEE J. Solid State Circuits Phil C. Knag, Gregory K. Chen, Huseyin Ekin Sumbul, Raghavan Kumar, Steven K. Hsu, Amit Agarwal, Monodeep Kar, Seongjong Kim, Mark A. Anders, Himanshu Kaul, Ram K. Krishnamurthy
2021	—	`conf`	A 7nm 4-Core AI Chip with 25.6TFLOPS Hybrid FP8 Training, 102.4TOPS INT4 Inference and Workload-Aware Throttling. ISSCC Ankur Agrawal, Sae Kyu Lee, Joel Silberman, Matthew M. Ziegler, Mingu Kang, Swagath Venkataramani, Nianzheng Cao, Bruce M. Fleischer, Michael Guillorn, Matt Cohen, Silvia M. Mueller, Jinwook Oh, Martin Lutz, Jinwook Jung, Siyu Koswatta, Ching Zhou, Vidhi Zalani, James Bonanno, Robert Casatuta, Chia-Yu Chen, Jungwook Choi, Howard Haynie, Alyssa Herbert, Radhika Jain, Monodeep Kar, Kyu-Hyoun Kim, Yulong Li, Zhibin Ren, Scot Rider, Marcel Schaal, Kerstin Schelm, Michael Scheuermann, Xiao Sun, Hung Tran, Naigang Wang, Wei Wang, Xin Zhang, Vinay Shah, Brian W. Curran, Vijayalakshmi Srinivasan, Pong-Fei Lu, Sunil Shukla, Leland Chang, Kailash Gopalakrishnan
2021	—	`conf`	Methodology of Assessing Information Leakage through Software-Accessible Telemetries. HOST Chen Liu, Monodeep Kar, Xueyang Wang, Nikhil Chawla, Neer Roggel, Bilgiday Yuce, Jason M. Fung
2021	A*	`conf`	RaPiD: AI Accelerator for Ultra-low Precision Training and Inference. ISCA Swagath Venkataramani, Vijayalakshmi Srinivasan, Wei Wang, Sanchari Sen, Jintao Zhang, Ankur Agrawal, Monodeep Kar, Shubham Jain, Alberto Mannari, Hoang Tran, Yulong Li, Eri Ogawa, Kazuaki Ishizaki, Hiroshi Inoue, Marcel Schaal, Mauricio J. Serrano, Jungwook Choi, Xiao Sun, Naigang Wang, Chia-Yu Chen, Allison Allain, James Bonanno, Nianzheng Cao, Robert Casatuta, Matthew Cohen, Bruce M. Fleischer, Michael Guillorn, Howard Haynie, Jinwook Jung, Mingu Kang, Kyu-Hyoun Kim, Siyu Koswatta, Sae Kyu Lee, Martin Lutz, Silvia M. Mueller, Jinwook Oh, Ashish Ranjan, Zhibin Ren, Scot Rider, Kerstin Schelm, Michael Scheuermann, Joel Silberman, Jie Yang, Vidhi Zalani, Xin Zhang, Ching Zhou, Matthew M. Ziegler, Vinay Shah, Moriyoshi Ohara, Pong-Fei Lu, Brian W. Curran, Sunil Shukla, Leland Chang, Kailash Gopalakrishnan
2021	J	`jnl`	Securing IoT Devices Using Dynamic Power Management: Machine Learning Approach. IEEE Internet Things J. Nikhil Chawla, Arvind Singh, Harshit Kumar, Monodeep Kar, Saibal Mukhopadhyay
2021	—	`conf`	VDPred: Predicting Voltage Droop for Power-Effient 3D Multi-core Processor Design. ICCAE He Xiao, Monodeep Kar, Saibal Mukhopadhyay, Sudhakar Yalamanchili
2020	—	`conf`	25.7 Time-Borrowing Fast Mux-D Scan Flip-Flop with On-Chip Timing/Power/VMIN Characterization Circuits in 10nm CMOS. ISSCC Amit Agarwal, Steven Hsu, Simeon Realov, Mark A. Anders, Gregory K. Chen, Monodeep Kar, Raghavan Kumar, Huseyin Sumbul, Phil C. Knag, Himanshu Kaul, Sanu Mathew, Mahesh Kumashikar, Ram Krishnamurthy, Vivek De
2020	—	`conf`	25.9 Reconfigurable Transient Current-Mode Global Interconnect Circuits in 10nm CMOS for High-Performance Processors with Wide Voltage-Frequency Operating Range. ISSCC Mark A. Anders, Himanshu Kaul, Seongjong Kim, Gregory K. Chen, Raghavan Kumar, Huseyin Ekin Sumbul, Phil C. Knag, Monodeep Kar, Steven K. Hsu, Amit Agarwal, Vikram B. Suresh, Sanu K. Mathew, Ram K. Krishnamurthy, Vivek De
2020	J	`jnl`	A 4900- $\mu$ m IEEE J. Solid State Circuits Raghavan Kumar, Vikram B. Suresh, Monodeep Kar, Sudhir Satpathy, Mark A. Anders, Himanshu Kaul, Amit Agarwal, Steven Hsu, Gregory K. Chen, Ram K. Krishnamurthy, Vivek De, Sanu K. Mathew
2020	—	`conf`	A 617 TOPS/W All Digital Binary Neural Network Accelerator in 10nm FinFET CMOS. VLSI Circuits Phil C. Knag, Gregory K. Chen, Huseyin Ekin Sumbul, Raghavan Kumar, Mark A. Anders, Himanshu Kaul, Steven K. Hsu, Amit Agarwal, Monodeep Kar, Seongjong Kim, Ram K. Krishnamurthy
2020	—	`conf`	A Ray-Casting Accelerator in 10nm CMOS for Efficient 3D Scene Reconstruction in Edge Robotics and Augmented Reality Applications. VLSI Circuits Monodeep Kar, Amit Agarwal, Steven Hsu, David Moloney, Gregory K. Chen, Raghavan Kumar, Huseyin Sumbul, Phil C. Knag, Mark A. Anders, Himanshu Kaul, Jonathan Byrne, Luca Sarti, Ram Krishnamurthy, Vivek De
2020	J	`jnl`	An Inductive Voltage Regulator With Overdrive Tracking Across Input Voltage in Cascoded Power Stage. IEEE Trans. Circuits Syst. Venkata Chaitanya Krishna Chekuri, Monodeep Kar, Arvind Singh, Anto Kavungal Davis, Mohamed Lamine Faycal Bellaredj, Madhavan Swaminathan, Saibal Mukhopadhyay
2020	J	`jnl`	Enhanced Power and Electromagnetic SCA Resistance of Encryption Engines via a Security-Aware Integrated All-Digital LDO. IEEE J. Solid State Circuits Arvind Singh, Monodeep Kar, Venkata Chaitanya Krishna Chekuri, Sanu K. Mathew, Anand Rajan, Vivek De, Saibal Mukhopadhyay
2020	—	`conf`	Low-Clock-Power Digital Standard Cell IPs for High-Performance Graphics/AI Processors in 10nm CMOS. VLSI Circuits Steven Hsu, Amit Agarwal, Simeon Realov, Mark A. Anders, Gregory K. Chen, Monodeep Kar, Raghavan Kumar, Huseyin Sumbul, Phil C. Knag, Himanshu Kaul, Vikram B. Suresh, Sanu Mathew, Iqbal Rajwani, Satish Damaraju, Ram Krishnamurthy, Vivek De
2019	—	`conf`	A 128b AES Engine with Higher Resistance to Power and Electromagnetic Side-Channel Attacks Enabled by a Security-Aware Integrated All-Digital Low-Dropout Regulator. ISSCC Arvind Singh, Monodeep Kar, Sanu Mathew, Anand Rajan, Vivek De, Saibal Mukhopadhyay
2019	—	`conf`	A 4900×m VLSI Circuits Raghavan Kumar, Vikram B. Suresh, Monodeep Kar, Sudhir Satpathy, Mark A. Anders, Himanshu Kaul, Amit Agarwal, Steven Hsu, Gregory K. Chen, Ram Krishnamurthy, Vivek De, Sanu Mathew
2019	—	`conf`	A 54% Power-Saving Static Fully-Interruptible Single-Phase-Clocked Shared-Keeper Flip-Flop in 14nm CMOS. A-SSCC Amit Agarwal, Steven Hsu, Monodeep Kar, Mark A. Anders, Himanshu Kaul, Raghavan Kumar, Vikram B. Suresh, Sanu Mathew, Ram Krishnamurthy, Vivek De
2019	—	`conf`	A Microwatt-Class Always-On Sensor Fusion Engine Featuring Ultra-Low-Power AOI Clocked Circuits in 14nm CMOS. VLSI Circuits Steven Hsu, Amit Agarwal, Monodeep Kar, Mark A. Anders, Himanshu Kaul, Raghavan Kumar, Sudhir Satpathy, Vikram B. Suresh, Sanu Mathew, Ram Krishnamurthy, Vivek De
2019	B	`conf`	Application Inference using Machine Learning based Side Channel Analysis. IJCNN Nikhil Chawla, Arvind Singh, Monodeep Kar, Saibal Mukhopadhyay
2019	J	`jnl`	Application Inference using Machine Learning based Side Channel Analysis. CoRR Nikhil Chawla, Arvind Singh, Monodeep Kar, Saibal Mukhopadhyay
2019	J	`jnl`	Autotuning of Integrated Inductive Voltage Regulator Using On-Chip Delay Sensor to Tolerate Process and Passive Variations. IEEE Trans. Very Large Scale Integr. Syst. Venkata Chaitanya Krishna Chekuri, Monodeep Kar, Arvind Singh, Saibal Mukhopadhyay
2019	J	`jnl`	Energy Efficient and Side-Channel Secure Cryptographic Hardware for IoT-Edge Nodes. IEEE Internet Things J. Arvind Singh, Nikhil Chawla, Jong Hwan Ko, Monodeep Kar, Saibal Mukhopadhyay
2019	—	`conf`	Extracting Side-Channel Leakage from Round Unrolled Implementations of Lightweight Ciphers. HOST Nikhil Chawla, Arvind Singh, Nael Mizanur Rahman, Monodeep Kar, Saibal Mukhopadhyay
2019	J	`jnl`	Improved Power/EM Side-Channel Attack Resistance of 128-Bit AES Engines With Random Fast Voltage Dithering. IEEE J. Solid State Circuits Arvind Singh, Monodeep Kar, Sanu K. Mathew, Anand Rajan, Vivek De, Saibal Mukhopadhyay
2019	A	`conf`	Mitigating Power Supply Glitch based Fault Attacks with Fast All-Digital Clock Modulation Circuit. DATE Arvind Singh, Monodeep Kar, Nikhil Chawla, Saibal Mukhopadhyay
2019	J	`jnl`	Multigated Carbon Nanotube Field Effect Transistors-Based Physically Unclonable Functions As Security Keys. IEEE Internet Things J. Nitish Kumar, Jialuo Chen, Monodeep Kar, Suresh K. Sitaraman, Saibal Mukhopadhyay, Satish Kumar
2018	J	`jnl`	Blindsight: Blinding EM Side-Channel Leakage using Built-In Fully Integrated Inductive Voltage Regulator. CoRR Monodeep Kar, Arvind Singh, Sanu Mathew, Santosh Ghosh, Anand Rajan, Vivek De, Raheem A. Beyah, Saibal Mukhopadhyay
2018	—	`conf`	Energy efficient and side-channel secure hardware architecture for lightweight cipher SIMON. HOST Arvind Singh, Nikhil Chawla, Monodeep Kar, Saibal Mukhopadhyay
2018	—	`—`	Exploiting fully integrated inductive voltage regulators to improve side channel resistance of encryption engines. Monodeep Kar
2018	A	`conf`	Exploiting on-chip power management for side-channel security. DATE Arvind Singh, Monodeep Kar, Sanu Mathew, Anand Rajan, Vivek De, Saibal Mukhopadhyay
2018	A	`conf`	Performance based tuning of an inductive integrated voltage regulator driving a digital core against process and passive variations. DATE Venakata Chaitanya Krishna Chekuri, Monodeep Kar, Arvind Singh, Saibal Mukhopadhyay
2018	J	`jnl`	Reducing Power Side-Channel Information Leakage of AES Engines Using Fully Integrated Inductive Voltage Regulator. IEEE J. Solid State Circuits Monodeep Kar, Arvind Singh, Sanu K. Mathew, Anand Rajan, Vivek De, Saibal Mukhopadhyay
2017	—	`conf`	8.1 Improved power-side-channel-attack resistance of an AES-128 core via a security-aware integrated buck voltage regulator. ISSCC Monodeep Kar, Arvind Singh, Sanu Mathew, Anand Rajan, Vivek De, Saibal Mukhopadhyay
2017	A	`conf`	A case for low frequency single cycle multi hop NoCs for energy efficiency and high performance. ICCAD Monodeep Kar, Tushar Krishna
2017	J	`jnl`	An All-Digital Fully Integrated Inductive Buck Regulator With A 250-MHz Multi-Sampled Compensator and a Lightweight Auto-Tuner in 130-nm CMOS. IEEE J. Solid State Circuits Monodeep Kar, Arvind Singh, Anand Rajan, Vivek De, Saibal Mukhopadhyay
2017	—	`conf`	Improved power side channel attack resistance of a 128-bit AES engine with random fast voltage dithering. ESSCIRC Arvind Singh, Monodeep Kar, Sanu Mathew, Anand Rajan, Vivek De, Saibal Mukhopadhyay
2017	A	`conf`	Invited paper: Low power requirements and side-channel protection of encryption engines: Challenges and opportunities. ISLPED Monodeep Kar, Arvind Singh, Sanu Mathew, Anand Rajan, Vivek De, Saibal Mukhopadhyay
2017	J	`jnl`	Reducing Side-Channel Leakage of Encryption Engines Using Integrated Low-Dropout Voltage Regulators. J. Hardw. Syst. Secur. Arvind Singh, Monodeep Kar, Sanu Mathew, Anand Rajan, Vivek De, Saibal Mukhopadhyay
2016	—	`conf`	(Invited paper) energy delivery for self-powered IoT devices. ASP-DAC Khondker Zakir Ahmed, Monodeep Kar, Saibal Mukhopadhyay
2016	—	`conf`	An integrated inductive VR with a 250MHz all-digital multisampled compensator and on-chip auto-tuning of coefficients in 130nm CMOS. ESSCIRC Monodeep Kar, Arvind Singh, Anand Rajan, Vivek De, Saibal Mukhopadhyay
2016	A	`conf`	Exploiting Fully Integrated Inductive Voltage Regulators to Improve Side Channel Resistance of Encryption Engines. ISLPED Monodeep Kar, Arvind Singh, Sanu Mathew, Anand Rajan, Vivek De, Saibal Mukhopadhyay
2016	—	`conf`	Integrated all-digital low-dropout regulator as a countermeasure to power attack in encryption engines. HOST Arvind Singh, Monodeep Kar, Anand Rajan, Vivek De, Saibal Mukhopadhyay
2016	C	`conf`	What does ultra low power requirements mean for side-channel secure cryptography? ICCD Monodeep Kar, Arvind Singh, Anand Rajan, Vivek De, Saibal Mukhopadhyay
2015	A	`conf`	Exploring power attack protection of resource constrained encryption engines using integrated low-drop-out regulators. ISLPED Arvind Singh, Monodeep Kar, Jong Hwan Ko, Saibal Mukhopadhyay
2014	—	`conf`	Impact of inductive integrated voltage regulator on the power attack vulnerability of encryption engines: A simulation study. CICC Monodeep Kar, Denny Lie, Marilyn Wolf, Vivek De, Saibal Mukhopadhyay
2014	A	`conf`	Impact of process variation in inductive integrated voltage regulator on delay and power of digital circuits. ISLPED Monodeep Kar, Sergio Carlo, Harish Kumar Krishnamurthy, Saibal Mukhopadhyay