Mojtaba Valinataj

21 papers C 4Journal 12Unranked 5
YearRankTypeTitle / Venue / Authors
2023 J jnl
High-speed binary coded decimal digit multipliers with multiple error detection.
Integr.
Zahra Yazdanian Amiri, Mojtaba Valinataj
2022 J jnl
Hierarchical multipliers: A framework for high-speed multiple error detecting architectures.
Microelectron. J.
Mojtaba Valinataj, Axel Jantsch
2022 — conf
Operational Conditions Analysis for Memristive Stateful Logics - A Study on IMPLY and TMSL.
NEWCAS
Roya Rahimi Disfani, Nima Taherinejad, Mojtaba Valinataj
2021 J jnl
Comments on "Improved designs of digit-by-digit decimal multiplier".
Integr.
Mojtaba Valinataj, Zahra Yazdanian Amiri
2021 J jnl
High-speed and low-cost carry select adders utilizing new optimized add-one circuit and multiplexer-based logic.
Integr.
Maytham Allahi Rudposhti, Mojtaba Valinataj
2019 J jnl
Parloom: A New Low-Power Set-Associative Instruction Cache Architecture Utilizing Enhanced Counting Bloom Filter and Partial Tags.
J. Circuits Syst. Comput.
Sajjad Rostami Sani, Mojtaba Valinataj, Saeideh Alinezhad Chamazcoti
2018 J jnl
A low-cost high-speed self-checking carry select adder with multiple-fault detection.
Microelectron. J.
Mojtaba Valinataj, Abbas Mohammadnezhad, Jari Nurmi
2018 J jnl
aPaRT: A Fast Meta-Heuristic Algorithm using Path-Relinking and Tabu Search for Allocating Machines to Operations in FJSP Problem.
Inteligencia Artif.
Hamid Jazayeriy, Sahar Bakhtar, Mojtaba Valinataj
2017 J jnl
Novel parity-preserving reversible logic array multipliers.
J. Supercomput.
Mojtaba Valinataj
2016 J jnl
A low-cost, fault-tolerant and high-performance router architecture for on-chip networks.
Microprocess. Microsystems
Mojtaba Valinataj, Mostafa Shahiri
2016 — conf
A reliable and high-performance Network-on-Chip router through decoupled resource sharing.
HPCS
Mostafa Shahiri, Mojtaba Valinataj, Amir M. Rahmani
2016 J jnl
Novel low-cost and fault-tolerant reversible logic adders.
Comput. Electr. Eng.
Mojtaba Valinataj, Mahboobeh Mirshekar, Hamid Jazayeri
2015 J jnl
Fault-tolerant carry look-ahead adder architectures robust to multiple simultaneous errors.
Microelectron. Reliab.
Mojtaba Valinataj
2014 J jnl
A novel self-checking carry lookahead adder with multiple error detection/correction.
Microprocess. Microsystems
Mojtaba Valinataj
2013 C conf
Enhanced fault-tolerant Network-on-Chip architecture using hierarchical agents.
DDECS
Mojtaba Valinataj, Pasi Liljeberg, Juha Plosila
2011 — conf
A fault-tolerant and hierarchical routing algorithm for NoC architectures.
NORCHIP
Mojtaba Valinataj, Pasi Liljeberg, Juha Plosila
2011 C conf
Evaluation of Fault-Tolerant Routing Methods for NoC Architectures.
DSD
Mojtaba Valinataj
2010 C conf
A fault-aware, reconfigurable and adaptive routing algorithm for NoC applications.
VLSI-SoC
Mojtaba Valinataj, Siamak Mohammadi
2010 C conf
A fault-tolerant and congestion-aware routing algorithm for Networks-on-Chip.
DDECS
Mojtaba Valinataj, Siamak Mohammadi, Juha Plosila, Pasi Liljeberg
2008 — conf
Inherent reliability evaluation of Networks-on-Chip based on analytical models.
SoC
Mojtaba Valinataj, Siamak Mohammadi, Saeed Safari
2007 — conf
Fault Tolerant Arithmetic Operations with Multiple Error Detection and Correction.
DFT
Mojtaba Valinataj, Saeed Safari