Mohsen Saneei

17 papers A* 1C 1Journal 14Unranked 1
YearRankTypeTitle / Venue / Authors
2021 J jnl
Evaluation of multi-level Bang-Bang phase detector with metastability effect using Markov chain.
Microelectron. J.
Sanaz Salem, Mohsen Saneei, Dariush Abbasi-Moghadam
2021 J jnl
Jitter Modeling in Digital CDR with Quantization Noise Analysis.
Circuits Syst. Signal Process.
Sanaz Salem, Mohsen Saneei, Dariush Abbasi-Moghadam
2020 J jnl
Jitter and metastability analysis and modeling of multilevel bang-bang phase detector.
Int. J. Circuit Theory Appl.
Sanaz Salem, Mohsen Saneei, Dariush Abbasi-Moghadam
2019 J jnl
All-digital delay line-based time difference amplifier in 65 nm CMOS technology.
IET Circuits Devices Syst.
Ramin Razmdideh, Mohsen Saneei
2019 J jnl
Design and analysis of differential ring voltage controlled oscillator for wide tuning range and low power applications.
Int. J. Circuit Theory Appl.
Shirin Askari, Mohsen Saneei
2018 J jnl
Fault-tolerant delay cell for ring oscillator application in 65 nm CMOS technology.
IET Circuits Devices Syst.
Sanaz Salem, Hamed Zandevakili, Ali Mahani, Mohsen Saneei
2018 J jnl
Low-power, latch-based multistage time-to-digital converter in 65 nm CMOS technology.
Int. J. Circuit Theory Appl.
Ramin Razmdideh, Mohsen Saneei
2015 J jnl
A novel low power and high speed double edge explicit pulse triggered level converter flip-flop.
Int. J. Circuit Theory Appl.
Ramin Razmdideh, Mohsen Saneei
2015 J jnl
New Design of Scan Flip-Flop to Increase Speed and Reduce Power Consumption.
J. Circuits Syst. Comput.
Ramin Razmdideh, Ali Mahani, Mohsen Saneei
2015 J jnl
Time-to-digital convertor based on resolution control.
IET Circuits Devices Syst.
Asma Dehghani, Mohsen Saneei, Ali Mahani
2015 J jnl
Two novel low power and very high speed pulse triggered flip-flops.
Int. J. Circuit Theory Appl.
Ramin Razmdideh, Mohsen Saneei
2013 J jnl
Probabilistic Transfer Matrix with mixed Binary-Decimal Coding for Logic Circuit Reliability Analysis.
J. Circuits Syst. Comput.
Hamed Zandevakili, Ali Mahani, Mohsen Saneei
2009 J jnl
Sign Bit Reduction Encoding For Low Power Applications.
J. Signal Process. Syst.
Mohsen Saneei, Ali Afzali-Kusha, Zainalabedin Navabi
2007 J jnl
Fast INC-XOR codec for low-power address buses.
IET Comput. Digit. Tech.
Hadi Parandeh-Afshar, Mohsen Saneei, Ali Afzali-Kusha, Massoud Pedram
2006 C conf
Low-power and low-latency cluster topology for local traffic NoCs.
ISCAS
Mohsen Saneei, Ali Afzali-Kusha, Zainalabedin Navabi
2006 — conf
Serial Bus Encoding for Low Power Application.
SoC
Mohsen Saneei, Ali Afzali-Kusha, Zainalabedin Navabi
2005 A* conf
Sign bit reduction encoding for low power applications.
DAC
Mohsen Saneei, Ali Afzali-Kusha, Zainalabedin Navabi