Mohan Vishwanath

23 papers B 1Misc 5Journal 6Unranked 11
YearRankTypeTitle / Venue / Authors
1998 J jnl
A Very Efficient Storage Structure for DWT and IDWT Filters.
J. VLSI Signal Process.
Robert Michael Owens, Mohan Vishwanath
1997 — conf
A progressive Ziv-Lempel algorithm for image compression.
SEQUENCES
Daniel Greene, Mohan Vishwanath, F. Frances Yao, Tong Zhang
1996 — conf
A Common Architecture For The DWT and IDWT.
ASAP
Mohan Vishwanath, Robert Michael Owens
1996 Misc conf
A low power video encoder with power, memory and bandwidth scalability.
VLSI Design
Navin Chaddha, Mohan Vishwanath
1996 J jnl
An optimal time multiplication free algorithm for edge detection on a mesh.
J. VLSI Signal Process.
Manjit Borah, Chetana Nagendra, Mohan Vishwanath, Robert Michael Owens, Mary Jane Irwin
1996 J jnl
Architectures for wavelet transforms: A survey.
J. VLSI Signal Process.
Chaitali Chakrabarti, Mohan Vishwanath, Robert Michael Owens
1996 — conf
Improving the performance of hierarchical vector quantization using segmentation.
ICIP (3)
Rajan L. Joshi, Mohan Vishwanath
1995 Misc conf
A survey of architectures for the discrete and continuous wavelet transforms.
ICASSP
Chaitali Chakrabarti, Mohan Vishwanath, Robert Michael Owens
1995 J jnl
Efficient realizations of the discrete and continuous wavelet transforms: from single chip implementations to mappings on SIMD array computers.
IEEE Trans. Signal Process.
Chaitali Chakrabarti, Mohan Vishwanath
1995 B conf
Hierarchical Vector Quantization of Perceptually Weighted Block Transforms.
Data Compression Conference
Navin Chaddha, Mohan Vishwanath, Philip A. Chou
1994 — conf
A VLSI architecture for real-time hierarchical encoding/decoding of video using the wavelet transform.
ICASSP (2)
Mohan Vishwanath, Chaitali Chakrabarti
1994 — conf
Algorithms and architectures for hierarchical compression of video.
ASAP
Mohan Vishwanath
1994 — conf
An Efficient Algorithm for Hierarchical Compression of Video.
ICIP (3)
Mohan Vishwanath, Philip A. Chou
1994 J jnl
The recursive pyramid algorithm for the discrete wavelet transform.
IEEE Trans. Signal Process.
Mohan Vishwanath
1993 — conf
A new blocked IIR algorithm.
ICASSP (3)
Chen-Mi Wu, Mohan Vishwanath, Robert Michael Owens, Mary Jane Irwin
1993 — conf
Edge detection using fine-grained parallelism in VLSI.
ICASSP (1)
Chetana Nagendra, Manjit Borah, Mohan Vishwanath, Robert Michael Owens, Mary Jane Irwin
1993 J jnl
The design and implementation of the Arithmetic Cube II, a VLSI signal processing system.
IEEE Trans. Very Large Scale Integr. Syst.
Robert Michael Owens, Thomas P. Kelliher, Mary Jane Irwin, Mohan Vishwanath, Raminder Singh Bajwa, Wen-Lin Yang
1992 Misc conf
An AT
ICASSP
Mohan Vishwanath, Robert Michael Owens
1992 — conf
Discrete wavelet transforms in VLSI.
ASAP
Mohan Vishwanath, Robert Michael Owens, Mary Jane Irwin
1992 Misc conf
ECube: An Efficient Architecture for Analyzing Time-Varying Spectra.
VLSI Design
Mohan Vishwanath, Robert Michael Owens, Mary Jane Irwin
1992 — conf
Implementing a family of high performance, micrograined architectures.
ASAP
Robert Michael Owens, Mary Jane Irwin, Thomas P. Kelliher, Mohan Vishwanath, Raminder Singh Bajwa
1991 — conf
The Arithmetic Cube: error analysis and simulation.
ASAP
Mohan Vishwanath, Robert Michael Owens, Mary Jane Irwin
1991 Misc conf
The arithmetic cube II: a second generation VLSI DSP processor.
ICASSP
Mary Jane Irwin, Robert Michael Owens, Thomas P. Kelliher, Kin-Ki Leung, Mohan Vishwanath