Mohammad Shihabul Haque

16 papers A* 1A 3C 1Misc 2Journal 7Unranked 2
YearRankTypeTitle / Venue / Authors
2020 J jnl
Contract-based Hierarchical Resilience Management for Cyber-Physical Systems.
CoRR
Mohammad Shihabul Haque, Daniel Jun Xian Ng, Arvind Easwaran, Karthik Thangamariappan
2018 C conf
A Self-Reconfiguring Cache Architecture to Improve Control Quality in Cyber-Physical Systems.
ISORC
Mohammad Shihabul Haque, Sriram Vasudevan, Alamuri Sriram Nihar, Arvind Easwaran, Akash Kumar, Y. C. Tay
2018 J jnl
Contract-Based Hierarchical Resilience Management for Cyber-Physical Systems.
Computer
Mohammad Shihabul Haque, Daniel Jun Xian Ng, Arvind Easwaran, Karthikeyan Thangamariappan
2018 J jnl
Predictability and Performance Aware Replacement Policy PVISAM for Unified Shared Caches in Real-time Multicores.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst.
Mohammad Shihabul Haque, Arvind Easwaran
2015 J jnl
Accelerating Non-volatile/Hybrid Processor Cache Design Space Exploration for Application Specific Embedded Systems.
CoRR
Mohammad Shihabul Haque, Ang Li, Akash Kumar, Qingsong Wei
2015 — conf
Accelerating non-volatile/hybrid processor cache design space exploration for application specific embedded systems.
ASP-DAC
Mohammad Shihabul Haque, Ang Li, Akash Kumar, Qingsong Wei
2015 J jnl
CIPARSim: Cache Intersection Property Assisted Rapid Single-pass FIFO Cache Simulation Technique.
CoRR
Mohammad Shihabul Haque, Jorgen Peddersen, Sri Parameswaran
2015 J jnl
DEW: A Fast Level 1 Cache Simulation Approach for Embedded Processors with FIFO Replacement Policy.
CoRR
Mohammad Shihabul Haque, Jorgen Peddersen, Andhi Janapsatya, Sri Parameswaran
2015 J jnl
TRISHUL: A Single-pass Optimal Two-level Inclusive Data Cache Hierarchy Selection Process for Real-time MPSoCs.
CoRR
Mohammad Shihabul Haque, Akash Kumar, Yajun Ha, Qiang Wu, Shaobo Luo
2013 — conf
TRISHUL: A single-pass optimal two-level inclusive data cache hierarchy selection process for real-time MPSoCs.
ASP-DAC
Mohammad Shihabul Haque, Akash Kumar, Yajun Ha, Qiang Wu, Shaobo Luo
2012 Misc conf
DIMSim: a rapid two-level cache simulation approach for deadline-based MPSoCs.
CODES+ISSS
Mohammad Shihabul Haque, Roshan G. Ragel, Jude Angelo Ambrose, Swarnalatha Radhakrishnan, Sri Parameswaran
2011 A conf
CIPARSim: Cache intersection property assisted rapid single-pass FIFO cache simulation technique.
ICCAD
Mohammad Shihabul Haque, Jorgen Peddersen, Sri Parameswaran
2010 A conf
DEW: A fast level 1 cache simulation approach for embedded processors with FIFO replacement policy.
DATE
Mohammad Shihabul Haque, Jorgen Peddersen, Andhi Janapsatya, Sri Parameswaran
2010 A conf
Rapid runtime estimation methods for pipelined MPSoCs.
DATE
Haris Javaid, Andhi Janapsatya, Mohammad Shihabul Haque, Sri Parameswaran
2010 A* conf
SCUD: a fast single-pass L1 cache simulation approach for embedded processors with round-robin replacement policy.
DAC
Mohammad Shihabul Haque, Jorgen Peddersen, Andhi Janapsatya, Sri Parameswaran
2009 Misc conf
SuSeSim: a fast simulation strategy to find optimal L1 cache configuration for embedded systems.
CODES+ISSS
Mohammad Shihabul Haque, Andhi Janapsatya, Sri Parameswaran