| Year | Rank | Type | Title / Venue / Authors |
|---|---|---|---|
| 2023 | — | conf |
ISQED
|
| 2023 | J | jnl |
CoRR
|
| 2023 | — | — |
|
| 2022 | — | conf |
AICAS
|
| 2022 | — | conf |
NorCAS
|
| 2022 | A | conf |
DATE
|
| 2020 | C | conf |
DSD
|
| 2020 | — | conf |
ICECS
|
| 2020 | C | conf |
DDECS
|
| 2019 | J | jnl |
Electron. Commer. Res.
|
| 2008 | — | conf |
ISQED
|
| 2008 | C | conf |
Generating RTL Synthesizable Code from Behavioral Testbenches for Hardware-Accelerated Verification.
DSD
|
| 2007 | Misc | conf |
VLSI Design
|
| 2006 | C | conf |
ISCAS
|