Mohammad Reza Kakoee

33 papers A 5C 6Journal 10Unranked 12

Year	Rank	Type	Title / Venue / Authors
2015	J	`jnl`	Architecture Support for Tightly-Coupled Multi-Core Clusters with Shared-Memory HW Accelerators. IEEE Trans. Computers Masoud Dehyadegari, Andrea Marongiu, Mohammad Reza Kakoee, Siamak Mohammadi, Nasser Yazdani, Luca Benini
2014	J	`jnl`	At-Speed Distributed Functional Testing to Detect Logic and Delay Faults in NoCs. IEEE Trans. Computers Mohammad Reza Kakoee, Valeria Bertacco, Luca Benini
2013	—	`conf`	A shared-FPU architecture for ultra-low power MPSoCs. Conf. Computing Frontiers Mohammad Reza Kakoee, Igor Loi, Luca Benini
2012	—	`conf`	A multi-banked shared-l1 cache architecture for tightly coupled processor clusters. ISSoC Mohammad Reza Kakoee, Vladimir Petrovic, Luca Benini
2012	A	`conf`	A resilient architecture for low latency communication in shared-L1 processor clusters. DATE Mohammad Reza Kakoee, Igor Loi, Luca Benini
2012	—	`conf`	A tightly-coupled multi-core cluster with shared-memory HW accelerators. ICSAMOS Masoud Dehyadegari, Andrea Marongiu, Mohammad Reza Kakoee, Luca Benini, Siamak Mohammadi, Nasser Yazdani
2012	J	`jnl`	Evaluation of GALS Methods in Scaled CMOS Technology: Moonrake Chip Experience. Int. J. Embed. Real Time Commun. Syst. Milos Krstic, Xin Fan, Eckhard Grass, Luca Benini, Mohammad Reza Kakoee, Christoph Heer, Birgit Sanders, Alessandro Strano, Davide Bertozzi
2012	J	`jnl`	Robust Near-Threshold Design With Fine-Grained Performance Tunability. IEEE Trans. Circuits Syst. I Regul. Pap. Mohammad Reza Kakoee, Luca Benini
2012	J	`jnl`	Row-based FBB: A design-time optimization for post-silicon tunable circuits. Microelectron. J. Mohammad Reza Kakoee, Ashoka Visweswara Sathanur, Antonio Pullini, Luca Benini
2012	J	`jnl`	Variation-Tolerant Architecture for Ultra Low Power Shared-L1 Processor Clusters. IEEE Trans. Circuits Syst. II Express Briefs Mohammad Reza Kakoee, Igor Loi, Luca Benini
2011	—	`conf`	A distributed and topology-agnostic approach for on-line NoC testing. NOCS Mohammad Reza Kakoee, Valeria Bertacco, Luca Benini
2011	A	`conf`	A fully-synthesizable single-cycle interconnection network for Shared-L1 processor clusters. DATE Abbas Rahimi, Igor Loi, Mohammad Reza Kakoee, Luca Benini
2011	J	`jnl`	Fine-Grained Power and Body-Bias Control for Near-Threshold Deep Sub-Micron CMOS Circuits. IEEE J. Emerg. Sel. Topics Circuits Syst. Mohammad Reza Kakoee, Luca Benini
2011	J	`jnl`	Low Latency and Energy Efficient Scalable Architecture for Massive NoCs Using Generalized de Bruijn Graph. IEEE Trans. Very Large Scale Integr. Syst. Mohammad Hosseinabady, Mohammad Reza Kakoee, Jimson Mathew, Dhiraj K. Pradhan
2011	—	`conf`	Moonrake chip - GALS demonstrator in 40 nm CMOS technology. SoC Milos Krstic, Xin Fan, Eckhard Grass, Christoph Heer, Birgit Sanders, Luca Benini, Mohammad Reza Kakoee, Alessandro Strano, Davide Bertozzi
2011	A	`conf`	ReliNoC: A reliable network for priority-based on-chip communication. DATE Mohammad Reza Kakoee, Valeria Bertacco, Luca Benini
2010	—	`conf`	A new physical routing approach for robust bundled signaling on NoC links. ACM Great Lakes Symposium on VLSI Mohammad Reza Kakoee, Igor Loi, Luca Benini
2010	A	`conf`	Automatic synthesis of near-threshold circuits with fine-grained performance tunability. ISLPED Mohammad Reza Kakoee, Ashoka Visweswara Sathanur, Antonio Pullini, Jos Huisken, Luca Benini
2009	—	`conf`	A floorplan-aware interactive tool flow for NoC design and synthesis. SoCC Mohammad Reza Kakoee, Federico Angiolini, Srinivasan Murali, Antonio Pullini, Ciprian Seiculescu, Luca Benini
2008	A	`conf`	De Bruijn Graph as a Low Latency Scalable Architecture for Energy Efficient Massive NoCs. DATE Mohammad Hosseinabady, Mohammad Reza Kakoee, Jimson Mathew, Dhiraj K. Pradhan
2008	—	`conf`	Enhancing the Testability of RTL Designs Using Efficiently Synthesized Assertions. ISQED Mohammad Reza Kakoee, Mohammad Riazati, Siamak Mohammadi
2008	C	`conf`	Generating RTL Synthesizable Code from Behavioral Testbenches for Hardware-Accelerated Verification. DSD Mohammad Reza Kakoee, Mohammad Riazati, Siamak Mohammadi
2008	J	`jnl`	Graph based test case generation for TLM functional verification. Microprocess. Microsystems Mohammad Reza Kakoee, Mohammad Hossein Neishaburi, Siamak Mohammadi
2007	C	`conf`	A HW/SW Architecture to Reduce the Effects of Soft-Errors in Real-Time Operating System Services. DDECS Mohammad Hossein Neishaburi, Mohammad Reza Kakoee, Masoud Daneshtalab, Saeed Safari, Zainalabedin Navabi
2007	C	`conf`	A New Approach for Design and Verification of Transaction Level Models. ISCAS Mohammad Reza Kakoee, Hamid Shojaei, Hassan Ghasemzadeh, Marjan Sirjani, Zainalabedin Navabi
2007	—	`conf`	Assertion based design error diagnosis for core-based SoCs. SoCC Mohammad Reza Kakoee, Mohammad Hossein Neishaburi, Masoud Daneshtalab, Saeed Safari
2007	C	`conf`	Functional Test-Case Generation by a Control Transaction Graph for TLM Verification. DSD Mohammad Reza Kakoee, Mohammad Hossein Neishaburi, Siamak Mohammadi
2007	J	`jnl`	HW/SW architecture for soft-error cancellation in real-time operating system. IEICE Electron. Express Mohammad Hossein Neishaburi, Mohammad Reza Kakoee, Masoud Daneshtalab, Saeed Safari
2007	C	`conf`	Improving Robustness of Real-Time Operating Systems (RTOS) Services Related to Soft-Errors. AICCSA Mohammad Hossein Neishaburi, Masoud Daneshtalab, Mohammad Reza Kakoee, Saeed Safari
2007	C	`conf`	On-Chip Verification of NoCs Using Assertion Processors. DSD Mohammad Reza Kakoee, Mohammad Hossein Neishaburi, Masoud Daneshtalab, Saeed Safari, Zainalabedin Navabi
2007	—	`conf`	Reliable network-on-chip based on generalized de Bruijn graph. HLDVT Mohammad Hosseinabady, Mohammad Reza Kakoee, Jimson Mathew, Dhiraj K. Pradhan
2006	—	`conf`	Modified Pseudo LRU Replacement Algorithm. ECBS Hassan Ghasemzadeh, Sepideh Mazrouee, Mohammad Reza Kakoee
2003	—	`conf`	Using Integer Equations for High Level Formal Verification Property Checking. ISQED Bijan Alizadeh, Mohammad Reza Kakoee