Mohammad Hosseinabady

51 papers A 5B 7C 6Misc 1Journal 18Unranked 14
YearRankTypeTitle / Venue / Authors
2021 J jnl
Sparse and dense matrix multiplication hardware for heterogeneous multi-precision neural networks.
Array
José L. Núñez-Yáñez, Mohammad Hosseinabady
2020 J jnl
A Streaming Dataflow Engine for Sparse Matrix-Vector Multiplication Using High-Level Synthesis.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst.
Mohammad Hosseinabady, José Luis Núñez-Yáñez
2020 J jnl
High-Performance Simultaneous Multiprocessing for Heterogeneous System-on-Chip.
CoRR
Kris Nikov, Mohammad Hosseinabady, Rafael Asenjo, Andrés Rodríguez, Angeles G. Navarro, José L. Núñez-Yáñez
2020 — conf
Run-Time Power Modelling in Embedded GPUs with Dynamic Voltage and Frequency Scaling.
PARMA-DITAM@HiPEAC
José L. Núñez-Yáñez, Kris Nikov, Kerstin Eder, Mohammad Hosseinabady
2020 J jnl
Run-Time Power Modelling in Embedded GPUs with Dynamic Voltage and Frequency Scaling.
CoRR
José L. Núñez-Yáñez, Kris Nikov, Kerstin Eder, Mohammad Hosseinabady
2020 — conf
Sparse Matrix-Dense Matrix Multiplication on Heterogeneous CPU+FPGA Embedded System.
PARMA-DITAM@HiPEAC
Mohammad Hosseinabady, José L. Núñez-Yáñez
2019 J jnl
Correction to: Simultaneous multiprocessing in a software-defined heterogeneous FPGA.
J. Supercomput.
José L. Núñez-Yáñez, Sam Amiri, Mohammad Hosseinabady, Andrés Rodríguez, Rafael Asenjo, Angeles G. Navarro, Darío Suárez Gracia, Ruben Gran
2019 J jnl
Heterogeneous FPGA+GPU Embedded Systems: Challenges and Opportunities.
CoRR
Mohammad Hosseinabady, Mohd Amiruddin Bin Zainol, José L. Núñez-Yáñez
2019 J jnl
Simultaneous multiprocessing in a software-defined heterogeneous FPGA.
J. Supercomput.
José L. Núñez-Yáñez, Sam Amiri, Mohammad Hosseinabady, Andrés Rodríguez, Rafael Asenjo, Angeles G. Navarro, Darío Suárez Gracia, Ruben Gran
2018 J jnl
Dynamic Energy Management of FPGA Accelerators in Embedded Systems.
ACM Trans. Embed. Comput. Syst.
Mohammad Hosseinabady, José Luis Núñez-Yáñez
2018 A conf
Multi-precision convolutional neural networks on heterogeneous hardware.
DATE
Sam Amiri, Mohammad Hosseinabady, Simon McIntosh-Smith, José L. Núñez-Yáñez
2018 J jnl
Parallelizing Workload Execution in Embedded and High-Performance Heterogeneous Systems.
CoRR
José L. Núñez-Yáñez, Mohammad Hosseinabady, Moslem Amiri, Andrés Rodríguez, Rafael Asenjo, Angeles G. Navarro, Ruben Gran Tejero, Darío Suárez Gracia
2018 B conf
Workload Partitioning Strategy for Improved Parallelism on FPGA-CPU Heterogeneous Chips.
FPL
Sam Amiri, Mohammad Hosseinabady, Andrés Rodríguez, Rafael Asenjo, Angeles G. Navarro, José L. Núñez-Yáñez
2017 B conf
A systematic approach to design and optimise streaming applications on FPGA using high-level synthesis.
FPL
Mohammad Hosseinabady, José Luis Núñez-Yáñez
2017 — conf
Pipelined Streaming Computation of Histogram in FPGA OpenCL.
PARCO
Mohammad Hosseinabady, José Luis Núñez-Yáñez
2017 — conf
Simultaneous Multiprocessing on a FPGA+CPU Heterogeneous System-On-Chip.
PARCO
José L. Núñez-Yáñez, Mohammad Hosseinabady, Andrés Rodríguez, Rafael Asenjo, Angeles G. Navarro, Ruben Gran Tejero, Darío Suárez Gracia
2016 J jnl
Energy Optimization in Commercial FPGAs with Voltage, Frequency and Logic Scaling.
IEEE Trans. Computers
José Luis Núñez-Yáñez, Mohammad Hosseinabady, Arash Beldachi
2015 B conf
Energy optimization of FPGA-based stream-oriented computing with power gating.
FPL
Mohammad Hosseinabady, José Luis Núñez-Yáñez
2015 B conf
Optimised OpenCL workgroup synthesis for hybrid ARM-FPGA devices.
FPL
Mohammad Hosseinabady, José Luis Núñez-Yáñez
2014 B conf
Run-time power gating in hybrid ARM-FPGA devices.
FPL
Mohammad Hosseinabady, José Luis Núñez-Yáñez
2012 — conf
Exploring dynamically reconfigurable multicore designs with NoRC designer.
HPCS
José L. Núñez-Yáñez, Arash Beldachi, Atukem Nabina, Mohammad Hosseinabady
2012 J jnl
Fast and low overhead architectural transaction level modelling for large-scale network-on-chip simulation.
IET Comput. Digit. Tech.
Mohammad Hosseinabady, José Luis Núñez-Yáñez
2012 J jnl
Run-time stochastic task mapping on a large scale network-on-chip with dynamically reconfigurable tiles.
IET Comput. Digit. Tech.
Mohammad Hosseinabady, José Luis Núñez-Yáñez
2011 J jnl
Low Latency and Energy Efficient Scalable Architecture for Massive NoCs Using Generalized de Bruijn Graph.
IEEE Trans. Very Large Scale Integr. Syst.
Mohammad Hosseinabady, Mohammad Reza Kakoee, Jimson Mathew, Dhiraj K. Pradhan
2011 — conf
Single-Event Transient Analysis in High Speed Circuits.
ISED
Mohammad Hosseinabady, Pejman Lotfi-Kamran, Jimson Mathew, Saraju P. Mohanty, Dhiraj K. Pradhan
2010 C conf
Effective modelling of large NoCs using SystemC.
ISCAS
Mohammad Hosseinabady, José L. Núñez-Yáñez
2010 C conf
SystemC Architectural Transaction Level Modelling for Large NoCs.
FDL
Mohammad Hosseinabady, José L. Núñez-Yáñez
2010 — conf
Task Dispersal Measurement in Dynamic Reconfigurable NoCs.
ISVLSI
Mohammad Hosseinabady, José Luis Núñez-Yáñez, Antonio Marcello Coppola
2009 — conf
Energy optimization in a Network-on-Chip with dynamically reconfigurable processing nodes.
CCA/ISIC
José L. Núñez-Yáñez, Mohammad Hosseinabady, Atukem Nabina, Izhar Zaidi
2009 B conf
Run-time resource management in fault-tolerant network on reconfigurable chips.
FPL
Mohammad Hosseinabady, José L. Núñez-Yáñez
2008 J jnl
A Selective Trigger Scan Architecture for VLSI Testing.
IEEE Trans. Computers
Mohammad Hosseinabady, Shervin Sharifi, Fabrizio Lombardi, Zainalabedin Navabi
2008 A conf
De Bruijn Graph as a Low Latency Scalable Architecture for Energy Efficient Massive NoCs.
DATE
Mohammad Hosseinabady, Mohammad Reza Kakoee, Jimson Mathew, Dhiraj K. Pradhan
2008 C conf
Fault tolerant bit parallel finite field multipliers using LDPC codes.
ISCAS
Jimson Mathew, Jawar Singh, Abusaleh M. Jabir, Mohammad Hosseinabady, Dhiraj K. Pradhan
2008 — conf
Fault-tolerant dynamically reconfigurable NoC-based SoC.
ASAP
Mohammad Hosseinabady, José L. Núñez-Yáñez
2007 Misc conf
A UML Based System Level Failure Rate Assessment Technique for SoC Designs.
VTS
Mohammad Hosseinabady, Mohammad Hossein Neishaburi, Pejman Lotfi-Kamran, Zainalabedin Navabi
2007 C conf
An Analytical Model for Reliability Evaluation of NoC Architectures.
IOLTS
Atefe Dalirsani, Mohammad Hosseinabady, Zainalabedin Navabi
2007 C conf
Analysis of System-Failure Rate Caused by Soft-Errors using a UML-Based Systematic Methodology in an SoC.
IOLTS
Mohammad Hosseinabady, Mohammad Hossein Neishaburi, Zainalabedin Navabi, Alfredo Benso, Stefano Di Carlo, Paolo Prinetto, Giorgio Di Natale
2007 J jnl
Low overhead DFT using CDFG by modifying controller.
IET Comput. Digit. Tech.
Mohammad Hosseinabady, Pejman Lotfi-Kamran, Fabrizio Lombardi, Zainalabedin Navabi
2007 J jnl
Low test application time resource binding for behavioral synthesis.
ACM Trans. Design Autom. Electr. Syst.
Mohammad Hosseinabady, Pejman Lotfi-Kamran, Zainalabedin Navabi
2007 — conf
Reliable network-on-chip based on generalized de Bruijn graph.
HLDVT
Mohammad Hosseinabady, Mohammad Reza Kakoee, Jimson Mathew, Dhiraj K. Pradhan
2007 J jnl
Simultaneous Reduction of Dynamic and Static Power in Scan Structures
CoRR
Shervin Sharifi, Javid Jaffari, Mohammad Hosseinabady, Ali Afzali-Kusha, Zainalabedin Navabi
2007 — conf
Single Event Upset Detection and Correction.
ICIT
Jawar Singh, Jimson Mathew, Mohammad Hosseinabady, Dhiraj K. Pradhan
2007 A conf
Using the inter- and intra-switch regularity in NoC switch testing.
DATE
Mohammad Hosseinabady, Atefe Dalirsani, Zainalabedin Navabi
2006 A conf
A concurrent testing method for NoC switches.
DATE
Mohammad Hosseinabady, Abbas Banaiyan, Mahdi Nazm Bojnordi, Zainalabedin Navabi
2006 J jnl
Scan-Based Structure with Reduced Static and Dynamic Power Consumption.
J. Low Power Electron.
Shervin Sharifi, Javid Jaffari, Mohammad Hosseinabady, Ali Afzali-Kusha, Zainalabedin Navabi
2006 B conf
Single-Event Upset Analysis and Protection in High Speed Circuits.
ETS
Mohammad Hosseinabady, Pejman Lotfi-Kamran, Giorgio Di Natale, Stefano Di Carlo, Alfredo Benso, Paolo Prinetto
2005 — conf
A Flow Graph Technique for DFT Controller Modification.
SoCC
Mohammad Hosseinabady, Pejman Lotfi-Kamran, Pedram A. Riahi, Fabrizio Lombardi, Zainalabedin Navabi
2005 A conf
Simultaneous Reduction of Dynamic and Static Power in Scan Structures.
DATE
Shervin Sharifi, Javid Jaffari, Mohammad Hosseinabady, Ali Afzali-Kusha, Zainalabedin Navabi
2005 — conf
TED+: a data structure for microprocessor verification.
ASP-DAC
Pejman Lotfi-Kamran, Mohammad Hosseinabady, Hamid Shojaei, Mehran Massoumi, Zainalabedin Navabi
2003 — conf
Reducing Test Power, Time and Data Volume in SoC Testing Using Selective Trigger Scan Architecture.
DFT
Shervin Sharifi, Mohammad Hosseinabady, Pedram A. Riahi, Zainalabedin Navabi
2003 C conf
Selective Trigger Scan Architecture for Reducing Power, Time and Data Volume in SoC Testing.
VLSI-SOC
Shervin Sharifi, Mohammad Hosseinabady, Zainalabedin Navabi