Mohammad A. Ahmed

11 papers C 1Journal 1Unranked 9
YearRankTypeTitle / Venue / Authors
2019 J jnl
Logical Effort Framework for CNFET-Based VLSI Circuits for Delay and Area Optimization.
IEEE Trans. Very Large Scale Integr. Syst.
Muhammad Ali, Mohammad A. Ahmed, Malgorzata Chrzanowska-Jeske
2016 — conf
Buffered Interconnects in 3D IC Layout Design.
SLIP
Mohammad A. Ahmed, Sucheta Mohapatra, Malgorzata Chrzanowska-Jeske
2016 — conf
Performance optimization and power efficiency in 3D IC with buffer insertion scheme.
SoCC
Mohammad A. Ahmed, Sucheta Mohapatra, Malgorzata Chrzanowska-Jeske
2015 C conf
Dynamic nets-to-TSVs assignment in 3D floorplanning.
ISCAS
Mohammad A. Ahmed, Sucheta Mohapatra, Malgorzata Chrzanowska-Jeske
2014 — conf
3D floorplanning with nets-to-TSVs assignment.
ICECS
Mohammad A. Ahmed, Sucheta Mohapatra, Malgorzata Chrzanowska-Jeske
2014 — conf
Delay and power optimization with TSV-aware 3D floorplanning.
ISQED
Mohammad A. Ahmed, Malgorzata Chrzanowska-Jeske
2014 — conf
Stochastic analysis of CNFET circuits using enhanced logical effort model in the presence of metallic tubes.
ICECS
Muhammad Ali, Mohammad A. Ahmed, Malgorzata Chrzanowska-Jeske
2014 — conf
TSVs in early layout design exploration for 3D ICs.
LASCAS
Mohammad A. Ahmed, Malgorzata Chrzanowska-Jeske
2013 — conf
TSV capacitance aware 3-D floorplanning.
3DIC
Mohammad A. Ahmed, Malgorzata Chrzanowska-Jeske
2012 — conf
Fast floorplanning for fixed-outline and nonrectangular regions.
ICECS
Mohammad A. Ahmed, Shantesh Pinge, Malgorzata Chrzanowska-Jeske
2012 — conf
TSV stress-aware performance and reliability analysis.
ICECS
Muhammad Ali, Mohammad A. Ahmed, Malgorzata Chrzanowska-Jeske