Mohamed Nekili

15 papers C 2Journal 5Unranked 8
YearRankTypeTitle / Venue / Authors
2012 J jnl
A novel theory on parallel repeater-insertion methodologies for long on-chip interconnects.
Int. J. Circuit Theory Appl.
Falah R. Awwad, Mohamed Nekili, Mohamad Sawan
2008 J jnl
On Modeling of Parallel Repeater-Insertion Methodologies for SoC Interconnects.
IEEE Trans. Circuits Syst. I Regul. Pap.
Falah R. Awwad, Mohamed Nekili, Venkatanarayana Ramachandran, Mohamad Sawan
2005 — conf
A novel 2 GHz multi-layer AMBA high-speed bus interconnect matrix for SoC platforms.
ISCAS (4)
Alexandre Landry, Mohamed Nekili, Yvon Savaria
2005 J jnl
Simultaneous adaptive wire adjustment and local topology modification for tuning a bounded-skew clock tree.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst.
Haydar Saaied, Dhamin Al-Khalili, Asim J. Al-Khalili, Mohamed Nekili
2004 — conf
Optimal partitioning of globally asychronous locally synchronous processor arrays.
ACM Great Lakes Symposium on VLSI
Adhir Upadhyay, Syed Rafay Hasan, Mohamed Nekili
2003 — conf
Adaptive wire adjustment for bounded skew Clock Distribution Network.
ASP-DAC
Haydar Saaied, Dhamin Al-Khalili, Asim J. Al-Khalili, Mohamed Nekili
2002 — conf
A novel double edge-triggered pulse-clocked TSPC D flip-flop for high-performance and low-power VLSI design applications.
ISCAS (5)
Bill Pontikakis, Mohamed Nekili
2002 — conf
Quadratic deferred-merge embedding algorithm for zero skew clock distribution network.
Timing Issues in the Specification and Synthesis of Digital Systems
Haydar Saaied, Dhamin Al-Khalili, Asim J. Al-Khalili, Mohamed Nekili
2002 — conf
Variable-segment & variable-driver parallel regeneration techniques for RLC VLSI interconnects.
ACM Great Lakes Symposium on VLSI
Falah R. Awwad, Mohamed Nekili
2001 — conf
Minimizing process-induced skew using delay tuning.
ISCAS (4)
Mohamed Nekili, Yvon Savaria, Guy Bois
1999 J jnl
Spatial characterization of process variations via MOS transistor time constants in VLSI and WSI.
IEEE J. Solid State Circuits
Mohamed Nekili, Yvon Savaria, Guy Bois
1998 — conf
Design of Clock Distribution Networks in Presence of Process Variations.
Great Lakes Symposium on VLSI
Mohamed Nekili, Yvon Savaria, Guy Bois
1997 J jnl
Pipelined H-trees for high-speed clocking of large integrated systems in presence of process variations.
IEEE Trans. Very Large Scale Integr. Syst.
Mohamed Nekili, Guy Bois, Yvon Savaria
1994 C conf
A Fast Low-Power Driver for Long Interconnections in VLSI Systems.
ISCAS
Mohamed Nekili, Yvon Savaria, Guy Bois
1993 C conf
Parallel Regeneration of Interconnections in VLSI & ULSI Circuits.
ISCAS
Mohamed Nekili, Yvon Savaria