Mohamed Megahed

14 papers A 1Journal 7Unranked 6
YearRankTypeTitle / Venue / Authors
2025 — conf
7.1 A 212.5Gb/s DSP-Based PAM-4 Transceiver with 50dB Loss Compensation for Large AI System Interconnects in 4nm FinFET.
ISSCC
Ehung Chen, Henry Park, Mohammed Abdullatif, Miguel Gandara, Ahmed ElShater, Amr Khashaba, Shih-Hao Huang, Tsz-Bin Liu, Atharav Atharav, Joonyeong Lee, Qaiser Nehal, Mohamed Megahed, Yusang Chun, Cheng-En Shieh, Vidhan Jolly, SoonWon Kwon, Hsin-Ta Chien, Ke-Chung Wu, Cheng-En Liu, Peng Yan, Po-Jui Li, Chun-Han Chen, Tzu-Shun Lin, Pei-Chieh Liu, Tamer A. Ali
2024 J jnl
An SNR-Enhanced 8-Ary (SNRE-8) Modulation Technique for Wireline Transceivers Using Pulse Width, Position, and Amplitude Modulation.
IEEE J. Solid State Circuits
Mohamed Megahed, Yusang Chun, Zhiping Wang, Tejasvi Anand
2023 J jnl
A Sub-μW Energy Harvester Architecture With Reduced Top/Bottom Plate Switching Loss Achieving 80.66% Peak Efficiency in 180-nm CMOS.
IEEE J. Solid State Circuits
Mohamed Megahed, Tejasvi Anand
2023 J jnl
Weight Prediction Using the Hybrid Stacked-LSTM Food Selection Model.
Comput. Syst. Sci. Eng.
Ahmed M. Elshewey, Mahmoud Y. Shams, Zahraa Tarek, Mohamed Megahed, El-Sayed M. El-Kenawy, Mohamed A. El-Dosuky
2022 J jnl
A PAM-8 Wireline Transceiver With Linearity Improvement Technique and a Time-Domain Receiver Side FFE in 65 nm CMOS.
IEEE J. Solid State Circuits
Yusang Chun, Mohamed Megahed, Ashwin Ramachandran, Tejasvi Anand
2022 — conf
A Single-Clock-Phase Sense Amplifier Architecture with 9x Smaller Clock-to-Q Delay Compared to the StrongARM & 6.3dB Lower Noise Compared to Double-Tail.
VLSI Technology and Circuits
Xiaohui Lin, Mohamed Megahed, Tejasvi Anand
2021 — conf
A 27 Gb/s 5.39 pJ/bit 8-ary Modulated Wireline Transceiver Using Pulse Width and Amplitude Modulation Achieving 9.5 dB SNR Improvement over PAM-8.
VLSI Circuits
Mohamed Megahed, Yusang Chun, Zhiping Wang, Tejasvi Anand
2021 — conf
A Machine Learning Inspired Transceiver with ISI-Resilient Data Encoding: Hybrid-Ternary Coding + 2-Tap FFE + CTLE + Feature Extraction and Classification for 44.7dB Channel Loss in 7.3pJ/bit.
VLSI Circuits
Zhiping Wang, Mohamed Megahed, Yusang Chun, Tejasvi Anand
2020 J jnl
An iPWM Line-Coding-Based Wireline Transceiver With Clock -Domain Encoding for Compensating Up To 27-dB Loss While Operating at 0.5-to-0.9 V and 3-to-16 Gb/s in 65-nm CMOS.
IEEE J. Solid State Circuits
Ashwin Ramachandran, Yusang Chun, Mohamed Megahed, Tejasvi Anand
2019 — conf
A Sub 1μW Switched Source + Capacitor Architecture Free of Top/Bottom Plate Parasitic Switching Loss Achieving Peak Efficiency of 80.66% at a Regulated 1.8V Output in 180nm.
CICC
Mohamed Megahed, Y. Ramadass, Tejasvi Anand
2019 J jnl
A Switched Capacitor Multiple Input Single Output Energy Harvester (Solar + Piezo) Achieving 74.6% Efficiency With Simultaneous MPPT.
IEEE Trans. Circuits Syst. I Regul. Pap.
Abhishekh Devaraj, Mohamed Megahed, Yutao Liu, Ashwin Ramachandran, Tejasvi Anand
2017 A conf
FA*IR: A Fair Top-k Ranking Algorithm.
CIKM
Meike Zehlike, Francesco Bonchi, Carlos Castillo, Sara Hajian, Mohamed Megahed, Ricardo Baeza-Yates
2017 J jnl
FA*IR: A Fair Top-k Ranking Algorithm.
CoRR
Meike Zehlike, Francesco Bonchi, Carlos Castillo, Sara Hajian, Mohamed Megahed, Ricardo Baeza-Yates
2016 — conf
12-Gb/s low-power voltage-mode driver for multi-standard serial-link applications.
ICECS
Mohamed Megahed, Mohamed R. M. Rizk, Sameh A. Ibrahim, Mohamed Dessouky