Mohamed Hassan

48 papers A 16B 5C 2Misc 3Journal 17Unranked 4

Year	Rank	Type	Title / Venue / Authors
2025	A	`conf`	Criticality and Requirement Aware Heterogeneous Coherence for Mixed Criticality Systems. DATE Safin Bayes, Mohamed Hassan
2025	Misc	`conf`	On the Time Predictability of AXI4. SAC Roger Pujol, Jaume Abella, Mohamed Hassan, Francisco J. Cazorla
2025	J	`jnl`	OpenDRAM: A Modular, High-performance Soft Memory Controller for DDR4 DRAM. ACM Trans. Reconfigurable Technol. Syst. Ali Abbasi, Danesh Germchi, Amin Katani, Mohamed Hassan, Rodolfo Pellizzoni
2025	—	`conf`	Stream-Aware Intelligent Memory Controller through HW/SW Co-Design. MEMSYS Abdelrhman Mohamed Abotaleb, Maziar Goudarzi, Tomasz S. Czajkowski, Reza Azimi, Mohamed Hassan
2025	J	`jnl`	The Case for HW/SW Harmony in Real-Time Systems: Tightening Memory Latency of Streaming Applications. ACM Trans. Embed. Comput. Syst. Abdelrhman Mohamed Abotaleb, Mohamed Hassan
2024	A	`conf`	A Framework for Explainable, Comprehensive, and Customizable Memory-Centric Workloads. ICCAD Mohamed Abuelala, Mohamed Hassan
2024	C	`conf`	Event Monitor Validation in High-Integrity Systems. DSD Roger Pujol, Sergi Vilardell, Enrico Mezzetti, Mohamed Hassan, Jaume Abella, Francisco J. Cazorla
2024	C	`conf`	HW/SW Collaborative Techniques for Accelerating TinyML Inference Time at No Cost. DSD Bailian Sun, Mohamed Hassan
2024	J	`jnl`	Octopus: A Cycle-Accurate Cache System Simulator. IEEE Comput. Archit. Lett. Mohamed Hossam, Salah Hessien, Mohamed Hassan
2024	A	`conf`	Shared Data Kills Real-Time Cache Analysis. How to Resurrect It? DATE Safin Bayes, Mohamed Hossam, Mohamed Hassan
2023	B	`conf`	A Tight Holistic Memory Latency Bound Through Coordinated Management of Memory Resources. ECRTS Shorouk Abdelhalim, Danesh Germchi, Mohamed Hossam, Rodolfo Pellizzoni, Mohamed Hassan
2023	J	`jnl`	DISCO: Time-Compositional Cache Coherence for Multi-Core Real-Time Embedded Systems. IEEE Trans. Computers Mohamed Hassan
2023	A	`conf`	Improving Timing-Related Guarantees for Main Memory in Multicore Critical Embedded Systems. RTSS Asier Fernández de Lecea, Mohamed Hassan, Enrico Mezzetti, Jaume Abella, Francisco J. Cazorla
2023	J	`jnl`	PISCOT: A Pipelined Split-Transaction COTS-Coherent Bus for Multi-Core Real-Time Systems. ACM Trans. Embed. Comput. Syst. Salah Hessien, Mohamed Hassan
2023	Misc	`conf`	The Case for tinyML in Healthcare: CNNs for Real-Time On-Edge Blood Pressure Estimation. SAC Bailian Sun, Safin Bayes, Abdelrhman Mohamed Abotaleb, Mohamed Hassan
2023	Misc	`conf`	Tracking Coherence-Related Contention Delays in Real-Time Multicore Systems. SAC Roger Pujol, Mohamed Hassan, Hamid Tabani, Jaume Abella, Francisco Javier Cazorla-Almeida
2022	B	`conf`	Parallelism-Aware High-Performance Cache Coherence with Tight Latency Bounds. ECRTS Reza Mirosanlou, Mohamed Hassan, Rodolfo Pellizzoni
2022	B	`conf`	Predictably and Efficiently Integrating COTS Cache Coherence in Real-Time Systems. ECRTS Mohamed Hossam, Mohamed Hassan
2022	—	`conf`	tinyCare: A tinyML-based Low-Cost Continuous Blood Pressure Estimation on the Extreme Edge. ICHI Khaled Ahmed, Mohamed Hassan
2021	A	`conf`	Demystifying the Characteristics of High Bandwidth Memory for Real-Time Systems. ICCAD Kazi Asifuzzaman, Mohamed Abuelala, Mohamed Hassan, Francisco J. Cazorla
2021	J	`jnl`	Designing Predictable Cache Coherence Protocols for Multi-Core Real-Time Systems. IEEE Trans. Computers Anirudh Mohan Kaushik, Mohamed Hassan, Hiren D. Patel
2021	A	`conf`	Duetto: Latency Guarantees at Minimal Performance Cost. DATE Reza Mirosanlou, Mohamed Hassan, Rodolfo Pellizzoni
2021	—	`conf`	DuoMC: Tight DRAM Latency Bounds with Shared Banks and Near-COTS Performance. MEMSYS Reza Mirosanlou, Mohamed Hassan, Rodolfo Pellizzoni
2021	A	`conf`	Empirical Evidence for MPSoCs in Critical Systems: The Case of NXP's T2080 Cache Coherence. DATE Roger Pujol, Hamid Tabani, Jaume Abella, Mohamed Hassan, Francisco J. Cazorla
2020	B	`conf`	Analysis of Memory-Contention in Heterogeneous COTS MPSoCs. ECRTS Mohamed Hassan, Rodolfo Pellizzoni
2020	A	`conf`	DRAMbulism: Balancing Performance and Predictability through Dynamic Pipelining. RTAS Reza Mirosanlou, Mohamed Hassan, Rodolfo Pellizzoni
2020	B	`conf`	Discriminative Coherence: Balancing Performance and Latency Bounds in Data-Sharing Multi-Core Real-Time Systems. ECRTS Mohamed Hassan
2020	J	`jnl`	MCsim: An Extensible DRAM Memory Controller Simulator. IEEE Comput. Archit. Lett. Reza Mirosanlou, Danlu Guo, Mohamed Hassan, Rodolfo Pellizzoni
2020	J	`jnl`	Reduced latency DRAM for multi-core safety-critical real-time systems. Real Time Syst. Mohamed Hassan
2020	A	`conf`	The Best of All Worlds: Improving Predictability at the Performance of Conventional Coherence with No Protocol Modifications. RTSS Salah Hessien, Mohamed Hassan
2019	A	`conf`	Enabling Predictable, Simultaneous and Coherent Data Sharing in Mixed Criticality Systems. RTSS Nivedita Sritharan, Anirudh M. Kaushik, Mohamed Hassan, Hiren D. Patel
2019	—	`conf`	Managing DRAM Interference in Mixed Criticality Embedded Systems. ICM Mohamed Hassan
2018	J	`jnl`	A Comparative Study of Predictable DRAM Controllers. ACM Trans. Embed. Comput. Syst. Danlu Guo, Mohamed Hassan, Rodolfo Pellizzoni, Hiren D. Patel
2018	J	`jnl`	Bounding DRAM Interference in COTS Heterogeneous MPSoCs for Mixed Criticality Systems. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. Mohamed Hassan, Rodolfo Pellizzoni
2018	J	`jnl`	Exposing Implementation Details of Embedded DRAM Memory Controllers through Latency-based Analysis. ACM Trans. Embed. Comput. Syst. Mohamed Hassan, Anirudh M. Kaushik, Hiren D. Patel
2018	J	`jnl`	Heterogeneous MPSoCs for Mixed-Criticality Systems: Challenges and Opportunities. IEEE Des. Test Mohamed Hassan
2018	J	`jnl`	MCXplore: Automating the Validation Process of DRAM Memory Controller Designs. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. Mohamed Hassan, Hiren D. Patel
2018	A	`conf`	On the Off-Chip Memory Latency of Real-Time Systems: Is DDR DRAM Really the Best Option? RTSS Mohamed Hassan
2018	J	`jnl`	On the Off-chip Memory Latency of Real-Time Systems: Is DDR DRAM Really the Best Option? CoRR Mohamed Hassan
2017	J	`jnl`	Heterogeneous MPSoCs for Mixed Criticality Systems: Challenges and Opportunities. CoRR Mohamed Hassan
2017	J	`jnl`	HourGlass: Predictable Time-based Cache Coherence Protocol for Dual-Critical Multi-Core Systems. CoRR Nivedita Sritharan, Anirudh M. Kaushik, Mohamed Hassan, Hiren D. Patel
2017	J	`jnl`	PMC: A Requirement-Aware DRAM Controller for Multicore Mixed Criticality Systems. ACM Trans. Embed. Comput. Syst. Mohamed Hassan, Hiren D. Patel, Rodolfo Pellizzoni
2017	A	`conf`	Predictable Cache Coherence for Multi-core Real-Time Systems. RTAS Mohamed Hassan, Anirudh M. Kaushik, Hiren D. Patel
2017	—	`—`	Predictable Shared Memory Resources for Multi-Core Real-Time Systems. Mohamed Hassan
2016	A	`conf`	Criticality- and Requirement-Aware Bus Arbitration for Multi-Core Mixed Criticality Systems. RTAS Mohamed Hassan, Hiren D. Patel
2016	A	`conf`	MCXplore: An automated framework for validating memory controller designs. DATE Mohamed Hassan, Hiren D. Patel
2015	A	`conf`	A framework for scheduling DRAM memory accesses for multi-core mixed-time critical systems. RTAS Mohamed Hassan, Hiren D. Patel, Rodolfo Pellizzoni
2015	A	`conf`	Reverse-engineering embedded memory controllers through latency-based analysis. RTAS Mohamed Hassan, Anirudh M. Kaushik, Hiren D. Patel