Mitsuru Shiozaki

34 papers A 2C 7Misc 1Journal 17Unranked 7
YearRankTypeTitle / Venue / Authors
2023 J jnl
Exploring Effect of Residual Electric Charges on Cryptographic Circuits: Extended Version.
IEICE Trans. Fundam. Electron. Commun. Comput. Sci.
Mitsuru Shiozaki, Takeshi Sugawara, Takeshi Fujino
2021 J jnl
Deep learning side-channel attack against hardware implementations of AES.
Microprocess. Microsystems
Takaya Kubota, Kota Yoshida, Mitsuru Shiozaki, Takeshi Fujino
2021 J jnl
Model Reverse-Engineering Attack against Systolic-Array-Based DNN Accelerator Using Correlation Power Analysis.
IEICE Trans. Fundam. Electron. Commun. Comput. Sci.
Kota Yoshida, Mitsuru Shiozaki, Shunsuke Okura, Takaya Kubota, Takeshi Fujino
2021 J jnl
Simple electromagnetic analysis attack based on geometric leak on ASIC implementation of ring-oscillator PUF.
J. Cryptogr. Eng.
Mitsuru Shiozaki, Takeshi Fujino
2020 C conf
Cause Analysis Method of Entropy Loss in Physically Unclonable Functions.
ISCAS
Mitsuru Shiozaki, Yohei Hori, Tatsuya Oyama, Masayoshi Shirahata, Takeshi Fujino
2020 J jnl
Entropy Estimation of Physically Unclonable Functions.
IACR Cryptol. ePrint Arch.
Mitsuru Shiozaki, Yohei Hori, Takeshi Fujino
2020 — conf
Exploring Effect of Residual Electric Charges on Cryptographic Circuits.
ASHES@CCS
Mitsuru Shiozaki, Takeshi Sugawara, Takeshi Fujino
2020 C conf
Model Reverse-Engineering Attack using Correlation Power Analysis against Systolic Array Based Neural Network Accelerator.
ISCAS
Kota Yoshida, Takaya Kubota, Shunsuke Okura, Mitsuru Shiozaki, Takeshi Fujino
2019 C conf
Deep Learning Side-Channel Attack Against Hardware Implementations of AES.
DSD
Takaya Kubota, Kota Yoshida, Mitsuru Shiozaki, Takeshi Fujino
2019 Misc conf
Model-Extraction Attack Against FPGA-DNN Accelerator Utilizing Correlation Electromagnetic Analysis.
FCCM
Kota Yoshida, Takaya Kubota, Mitsuru Shiozaki, Takeshi Fujino
2019 — conf
Simple Electromagnetic Analysis Attacks based on Geometric Leak on an ASIC Implementation of Ring-Oscillator PUF.
ASHES@CCS
Mitsuru Shiozaki, Takeshi Fujino
2018 — conf
A Dynamic Soft-Decision Fuzzy Extractor for a CMOS Image Sensor PUF.
ISPACS
Shunsuke Okura, Ryota Ishiki, Masayoshi Shirahata, Takaya Kubota, Mitsuru Shiozaki, Kenichiro Ishikawa, Isao Takayanagi, Takeshi Fujino
2017 — conf
Malicious CAN-message attack against advanced driving assistant system.
HOST
Mitsuru Shiozaki, Takaya Kubota, Masashi Nakano, Yuuki Nakazawa, Takeshi Fujino
2017 J jnl
Tamper-resistant cryptographic hardware.
IEICE Electron. Express
Takeshi Fujino, Takaya Kubota, Mitsuru Shiozaki
2015 J jnl
Reversing stealthy dopant-level circuits.
J. Cryptogr. Eng.
Takeshi Sugawara, Daisuke Suzuki, Ryoichi Fujii, Shigeaki Tawa, Ryohei Hori, Mitsuru Shiozaki, Takeshi Fujino
2015 C conf
Tamper-resistant authentication system with side-channel attack resistant AES and PUF using MDR-ROM.
ISCAS
Mitsuru Shiozaki, Takaya Kubota, Tsunato Nakai, Akihiro Takeuchi, Takashi Nishimura, Takeshi Fujino
2014 J jnl
Diffusion Programmable Device : The device to prevent reverse engineering.
IACR Cryptol. ePrint Arch.
Mitsuru Shiozaki, Ryohei Hori, Takeshi Fujino
2014 J jnl
On measurable side-channel leaks inside ASIC design primitives.
J. Cryptogr. Eng.
Takeshi Sugawara, Daisuke Suzuki, Minoru Saeki, Mitsuru Shiozaki, Takeshi Fujino
2014 A conf
Reversing Stealthy Dopant-Level Circuits.
CHES
Takeshi Sugawara, Daisuke Suzuki, Ryoichi Fujii, Shigeaki Tawa, Ryohei Hori, Mitsuru Shiozaki, Takeshi Fujino
2014 J jnl
Reversing Stealthy Dopant-Level Circuits.
IACR Cryptol. ePrint Arch.
Takeshi Sugawara, Daisuke Suzuki, Ryoichi Fujii, Shigeaki Tawa, Ryohei Hori, Mitsuru Shiozaki, Takeshi Fujino
2014 J jnl
Security Evaluation of RG-DTM PUF Using Machine Learning Attacks.
IEICE Trans. Fundam. Electron. Commun. Comput. Sci.
Mitsuru Shiozaki, Kousuke Ogawa, Kota Furuhashi, Takahiko Murayama, Masaya Yoshikawa, Takeshi Fujino
2014 C conf
Side-channel attack resistant AES cryptographic circuits with ROM reducing address-dependent EM leaks.
ISCAS
Tsunato Nakai, Megumi Shibatani, Mitsuru Shiozaki, Takaya Kubota, Takeshi Fujino
2014 J jnl
Unified Coprocessor Architecture for Secure Key Storage and Challenge-Response Authentication.
IEICE Trans. Fundam. Electron. Commun. Comput. Sci.
Koichi Shimizu, Daisuke Suzuki, Toyohiro Tsurumaru, Takeshi Sugawara, Mitsuru Shiozaki, Takeshi Fujino
2013 — conf
A stable key generation from PUF responses with a Fuzzy Extractor for cryptographic authentications.
GCCE
Masato Taniguchi, Mitsuru Shiozaki, Hiroshi Kubo, Takeshi Fujino
2013 A conf
On Measurable Side-Channel Leaks Inside ASIC Design Primitives.
CHES
Takeshi Sugawara, Daisuke Suzuki, Minoru Saeki, Mitsuru Shiozaki, Takeshi Fujino
2013 J jnl
On Measurable Side-Channel Leaks inside ASIC Design Primitives.
IACR Cryptol. ePrint Arch.
Takeshi Sugawara, Daisuke Suzuki, Minoru Saeki, Mitsuru Shiozaki, Takeshi Fujino
2012 C conf
Efficient DPA-Resistance Verification Method with Smaller Number of Power Traces on AES Cryptographic Circuit.
DSD
Hiroki Ito, Mitsuru Shiozaki, Anh-Tuan Hoang, Takeshi Fujino
2012 J jnl
High Uniqueness Arbiter-Based PUF Circuit Utilizing RG-DTM Scheme for Identification and Authentication Applications.
IEICE Trans. Electron.
Mitsuru Shiozaki, Kota Furuhashi, Takahiko Murayama, Akitaka Fukushima, Masaya Yoshikawa, Takeshi Fujino
2011 — conf
Implementation and verification of DPA-resistant cryptographic DES circuit using Domino-RSL.
HOST
Katsuhiko Iwai, Mitsuru Shiozaki, Anh-Tuan Hoang, Kenji Kojima, Takeshi Fujino
2011 C conf
The arbiter-PUF with high uniqueness utilizing novel arbiter circuit with Delay-Time Measurement.
ISCAS
Kota Furuhashi, Mitsuru Shiozaki, Akitaka Fukushima, Takahiko Murayama, Takeshi Fujino
2007 — conf
12GHz Low-Area-Overhead Standing-Wave Clock Distribution with Inductively-Loaded and Coupled Technique.
ISSCC
Mamoru Sasaki, Mitsuru Shiozaki, Atsushi Mori, Atsushi Iwata, Hiroaki Ikeda
2006 J jnl
20GHz uniform-phase uniform-amplitude standing-wave clock distribution.
IEICE Electron. Express
Mitsuru Shiozaki, Mamoru Sasaki, Atsushi Mori, Atsushi Iwata, Hiroaki Ikeda
2005 J jnl
A 2.7 Gcps and 7-Multiplexing CDMA Serial Communication Chip Using Two-Step Synchronization Technique.
IEICE Trans. Electron.
Mitsuru Shiozaki, Toru Mukai, Masahiro Ono, Mamoru Sasaki, Atsushi Iwata
2005 J jnl
A 2.7 Gcps and 7-Multiplexing CDMA Serial Communication Chip for Real-Time Robot Control with Multiprocessors.
J. Robotics Mechatronics
Mitsuru Shiozaki, Toru Mukai, Masahiro Ono, Mamoru Sasaki, Atsushi Iwata