Mitsuru Hiraki

15 papers A 1C 1Journal 8Unranked 5
YearRankTypeTitle / Venue / Authors
2026 J jnl
Two-Dimensional NHA-Based Super-Resolution Technique for Millimeter-Wave FMCW Radar With Limited Channels.
IEEE Access
Shotaro Koyama, Taisei Matsuyama, Junpei Tsutsumi, Takumu Ikenaga, Iori Ishibitsu, Shota Sato, Yuji Motoda, Hiroyuki Kondo, Mitsuru Hiraki, Masaya Hasegawa, Shigeki Hirobayashi, Kazuo Yoshida
2023 — conf
An On-Chip DC-DC Converter and Power Management System Achieving Zero Standby-to-Active Transition Time in MCU.
A-SSCC
Toyohiro Shimogawa, Makoto Nonaka, Toma Ogata, Toshiki Kiryu, Yasuto Igarashi, Kosuke Yayama, Masahiro Kitamura, Hiromichi Ishikura, Mitsuru Hiraki, Masao Ito, Takashi Kono
2021 — conf
A CMOS Image Sensor and an AI Accelerator for Realizing Edge-Computing-Based Surveillance Camera Systems.
VLSI Circuits
Fukashi Morishita, Norihito Kato, Satoshi Okubo, Takao Toi, Mitsuru Hiraki, Sugako Otani, Hideaki Abe, Yuji Shinohara, Hiroyuki Kondo
2020 — conf
A High-Precision Analog Front End Integrated in a 32bit Microcontroller for Industrial Sensing Applications.
A-SSCC
Koji Yoichi, Sugako Otani, Kazutoshi Tsuda, Naoya Tokimoto, Hideki Kamegawa, Yoshihisa Satou, Shioto Tanaka, Hideki Otsu, Mitsuru Hiraki, Masao Ito, Mitsuya Fukazawa, Hiroyuki Kondo
2018 — conf
A Capacitance-to-Digital Converter Integrated in a 32bit Microcontroller for 3D Gesture Sensing.
A-SSCC
Mitsuru Hiraki, Sugako Otani, Masao Ito, Takuya Mizokami, Masahiro Araki, Hiroyuki Kondo
2004 J jnl
A low-power microcontroller having a 0.5-μA standby current on-chip regulator with dual-reference scheme.
IEEE J. Solid State Circuits
Mitsuru Hiraki, Kenichi Fukui, Takayasu Ito
2002 J jnl
A 63-μW standby power microcontroller with on-chip hybrid regulator scheme.
IEEE J. Solid State Circuits
Mitsuru Hiraki, Takayasu Ito, Atsushi Fujiwara, Taichi Ohashi, Tetsuro Hamano, Takaaki Noda
1999 — conf
Pre-silicon parameter generation methodology using BSIM3 for device/circuit concurrent design.
CICC
Mikako Miyama, Shiro Kamohara, Mitsuru Hiraki, Kazunori Onozawa, Hisaaki Kunitomo
1997 J jnl
Instruction buffering to reduce power in processors for signal processing.
IEEE Trans. Very Large Scale Integr. Syst.
Raminder Singh Bajwa, Mitsuru Hiraki, Hirotsugu Kojima, Douglas J. Gorny, Ken-ichi Nitta, Avadhani Shridhar, Koichi Seki, Katsuro Sasaki
1996 A conf
Stage-skip pipeline: a low power processor architecture using a decoded instruction buffer.
ISLPED
Mitsuru Hiraki, Raminder Singh Bajwa, Hirotsugu Kojima, Douglas J. Gorny, Ken-ichi Nitta, Avadhani Shridhar, Katsuro Sasaki, Koichi Seki
1995 J jnl
Data-dependent logic swing internal bus architecture for ultralow-power LSI's.
IEEE J. Solid State Circuits
Mitsuru Hiraki, Hirotsugu Kojima, Hitoshi Misawa, Takashi Akazawa, Yuji Hatano
1992 J jnl
3.3-V BiCMOS circuit techniques for 250-MHz RISC arithmetic modules.
IEEE J. Solid State Circuits
Kazuo Yano, Mitsuru Hiraki, Shoji Shukuri, M. Hanawa, Masato Suzuki, S. Morita, A. Kawamata, Nagatoshi Ohki, Takashi Nishida, Koichi Seki
1992 J jnl
A 1.5-V full-swing BiCMOS logic circuit.
IEEE J. Solid State Circuits
Mitsuru Hiraki, Kazuo Yano, Masataka Minami, Kazushige Sato, Nozomu Matsuzaki, Atsuo Watanabe, Takashi Nishida, Katsuro Sasaki, Koichi Seki
1991 C conf
On-Chip Multiple Superscalar Processors with Secondary Cache Memories.
ICCD
M. Hanawa, Tadahiko Nishimukai, O. Nishii, Masato Suzuki, Kazuo Yano, Mitsuru Hiraki, Shoji Shukuri, Takashi Nishida
1991 J jnl
Quasi-complementary BiCMOS for sub-3-V digital circuits.
IEEE J. Solid State Circuits
Kazuo Yano, Mitsuru Hiraki, Shoji Shukuri, Yasuo Onose, Mitsuru Hirao, Nagatoshi Ohki, Takashi Nishida, Koichi Seki, Katsuhiro Shimohigashi